NXP Semiconductors Data Sheet: Technical Data KL82P121M72SF0 Rev. 3, 08/2016 Kinetis KL82 Microcontroller 72 MHz ARM® Cortex®-M0+ with 128 KB Flash and 96 KB SRAM The KL82 MCU family's high performance, encryption features and ultra-low power capabilities extend its reach beyond traditional mPOS pin pads and terminals into more powerrestricted payment applications, such as smartphone and tablet attach readers, as well as those embedded in wearable technology.
I/O • Memory protection unit • SRAM bit-banding Clocks • 48 MHz high accuracy (up to 0.
2. To find the associated resource, go to http://www.nxp.com and perform a search using this term with the "x" replaced by the revision of the device you are using. Kinetis KL82 Microcontroller, Rev.
Table of Contents 1 Ordering information............................................................... 5 2 Overview................................................................................. 5 2.1 System features...............................................................7 2.1.1 ARM Cortex-M0+ core...................................... 7 2.1.2 NVIC..................................................................7 2.1.3 AWIC.................................................................7 2.1.
Ordering information 1 Ordering information The following chips are available for ordering. Table 1.
Overview GPIOA GPIOB GPIOC Cortex M0+ GPIOE TSI0 S0 IOPORT ADC0(16-bit 16-ch) 32 KB ROM M2 DMA MUX DMA M3 USB FS/LS Crossbar switch NVIC S1 CMP0 96 KB RAM Bit Band S3 QSPI0 S2a 2 KB USB SRAM S2b BME Peripheral Bridge(Bus Clock - Max 24MHZ) CM0+ core System memory protection unit (MPU) M0 Debug (SWD) GPIOD 128 KB Flash FMC Slave Master 1.
Overview 2.1 System features The following sections describe the high-level system features. 2.1.1 ARM Cortex-M0+ core The enhanced ARM Cortex M0+ is the member of the Cortex-M series of processors targeting microcontroller cores focused on very cost sensitive, low power applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also has hardware debug functionality including support for simple program trace capability.
Overview Table 2.
Overview This device contains a 32-byte register file that is powered in all power modes. Also, it retains contents during low power modes and is reset only during a power-on reset. 2.1.5 Reset and boot The following table lists all the reset sources supported by this device. NOTE In the following table, Y means the specific module, except for the registers, bits or conditions mentioned in the footnote, is reset by the corresponding Reset source.
Overview The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR) to relocate the exception vector table after reset. This device supports booting from: • internal flash • ROM The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows the user to customize the operation of the MCU at boot time. The register contains readonly bits that are loaded from the NVM's option byte in the flash configuration field. Below is boot flow chart for this device.
Overview If booting from ROM, the device executes in boot loader mode or proceeds with a secondary boot to a QSPI device connected to QSPI0. 2.1.6 Clock options This chip provides a wide range of sources to generate the internal clocks. These sources include internal resistor capacitor (IRC) oscillators, external oscillators, external clock sources, ceramic resonators, phase-locked loop (PLL) and frequencylocked loop (FLL).
Overview The phase-locked loop (PLL) can generate up to 144 MHz high speed, low jitter clock with 8–16 MHz internal or external reference clock. The PLL can be used as the system clock or clock source for other on-chip modules. For more details on the clock operations and configurations, see Reference Manual.
Overview The following table summarizes the clocks associated with each module. Table 4.
Overview Table 4.
Overview 2.1.8 Power management The Power Management Controller (PMC) expands upon ARM’s operational modes of Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can be used to optimize current consumption for a wide range of applications. The WFI or WFE instruction invokes a Wait or a Stop mode, depending on the current configuration. For more information on ARM’s operational modes, See the ARM® Cortex User Guide.
Overview Table 6. Peripherals states in different operational modes Core mode Run mode Sleep mode Deep sleep Device mode Descriptions High Speed Run In HSRun mode, MCU is able to operate at a faster frequency, all device modules are operational. Run In Run mode, all device modules are operational. Very Low Power Run In VLPR mode, all device modules are operational at a reduced frequency except the Low Voltage Detect (LVD) monitor, which is disabled.
Overview This device uses 25 external wakeup pin inputs and five internal modules as wakeup sources to the LLWU module. The following is internal peripheral and external pin inputs as wakeup sources to the LLWU module. Table 7.
Overview Table 7. Wakeup sources for LLWU inputs (continued) LLWU pins Module sources or pin names LLWU_M1IF CMP0 LLWU_M2IF Reserved LLWU_M3IF Reserved LLWU_M4IF TSI02 LLWU_M5IF RTC alarm LLWU_M6IF Reserved LLWU_M7IF RTC second 1. A wakeup source of LLWU, USB0_DP or USB0_DM is available only when the chip is in USB host mode. 2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU_ME[WUMEn] (n=0-7) bit enables the internal module flag a wakeup inputs.
Overview 2.1.12 Watch dog The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. The WDOG has the following features: • Clock source input independent from CPU/bus clock. Choice between low-power oscillator (LPO) and external system clock. • Unlock sequence for allowing updates to write-once WDOG control/configuration bits. • All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked.
Overview 2.2.2 eDMA and DMAMUX The eDMA controller module enables fast transfers of data, which provides an efficient way to move blocks of data with minimal processor interaction. The eDMA controller in this device implements eight channels which can be routed from up to 63 DMA request sources through DMA MUX module. Some of the peripheral request sources have asynchronous eDMA capability which can be used to wake MCU from Stop mode.
Overview • Support selectable trigger input to optionally reset or cause the counter to start or stop incrementing • Support the generation of hardware triggers when the counter overflows and per channel 2.2.4 ADC this device contains one ADC module. This ADC module supports hardware triggers from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock.
Overview • • • • Bandgap on only, used for stabilization and startup High power buffer mode Low-power buffer mode Buffer disabled A 100 nF capacitor must always be connected between VERF output (VREFO) pin and VSSA if the VREF is used. This capacitor must be as close to VREFO pin as possible. 2.2.6 CMP The device contains one high-speed comparator and two 8-input multiplexers for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes.
Overview 2.2.7 RTC The RTC is an always powered-on block that remains active in all low power modes. The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator or clock directly from RTC_CLKIN pin. RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all RTC registers.
Overview 2.2.9 LPTMR The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter.
Overview • Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4x to 32x • Transmit and receive baud rate can operate asynchronous to the bus clock • Interrupt, DMA or polled operation • Hardware parity generation and checking • Programmable 8-bit, 9-bit or 10-bit character length • Programmable 1-bit or 2-bit stop bits • Three receiver wakeup methods: idle line wakeup, address mark wakeup, receive data match • Automatic address matching to reduce ISR overhead • Option
Overview 2.2.13 I2C This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer features, and address match to wake MCU from the low power mode. I2C modules support DMA transfer, and the interrupt condition can trigger DMA request when DMA function is enabled.
Overview • IRC48M with clock-recovery is supported to eliminate the 48 MHz crystal. It is used for USB device-only implementation. • Keep-alive feature is supported to power down system bus and CPU. USB can respond to IN with NAK and wake up for SETUP/OUT. 2.2.15 FlexIO The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to LPUART, I2C, SPI, I2S, Camera IF, LCD RGB, PWM/ Waveform generation.
Overview • Vin can be selected from two reference sources • Static operation in Normal Stop mode • 16-word data buffer supported with configurable watermark and multiple operation modes • DMA support 2.2.17 EMV-SIM The EMV_SIM (Euro/Mastercard/Visa/SIM Serial Interface Module) is designed to facilitate communication to Smart Cards compatible to the EMV ver4.3 standard (Book 1) and Smart Cards compatible with ISO/IEC 7816-3 Standard.
Overview • Automatic power down of port logic on Smart Card presence detect • Support for 8-bit LRC and 16-bit CRC generation for bytes sent out from transmitter and checking incoming message checksum for receiver 2.2.18 LTC LP Trusted Cryptography (LTC) is a hardware accelerate module dedicate for the popular encryption algorithm.
Memory map • High sensitivity change with 16-bit resolution register • Configurable up to 4096 scan times. • Support DMA data transfer 2.2.21 QuadSPI The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to one single or two external serial flash devices, each with up to eight bidirectional data lines. This device contains one QSPI module, which supports singles, dual, quad or octal data lines in single (SDR) or double (DDR) data rate configurations.
Memory map 0x4000_0000 0x4000_8000 0x4000_9000 0x4000_A000 0x4000_D000 0x4000_E000 0x4000_F000 0x4001_0000 0x4002_0000 0x4002_1000 0x4002_2000 0x4002_4000 0x4002_5000 0x4002_6000 0x4002_C000 0x4002_D000 0x4002_E000 0x4003_2000 0x0000_0000 Flash 0x0000_0000 0x03FF_FFFF Code space 0x0400_0000 0x1C00_0000 Reserved 0x1C00_0000 ROM Boot ROM 0x1C00_7FFF 0x1C00_8000 Reserved 0x1FFF_A000 0x1FFF_A000 SRAM _L Data Space 0x2002_0000 Reserved 0x4000_0000 0x400F_F000 0x6000_0000 0x6700_0000 0x7000_0000 SR
Pinouts 4 Pinouts 4.1 KL82 signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
Pinouts 121 100 80 64 64 MAP LQFP LQFP MAP LQFP BGA BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 TPM0_CH5 ALT4 ALT5 ALT6 ALT7 FXIO0_D10 EMVSIM0_ CLK SWD_CLK J1 19 16 F2 12 USB_VDD USB_VDD USB_VDD J2 20 — — — NC NC NC — 21 — — — NC K2 — — — — ADC0_DP0 ADC0_DP0 ADC0_DP0 K1 — — — — ADC0_DM0 ADC0_DM0 ADC0_DM0 F5 22 17 G2 13 VDDA VDDA VDDA G5 23 18 H3 14 VREFH VREFH VREFH G6 24 19 H2 15 VREFL VREFL VREFL F6 25 20 G1 16 VSSA VSSA VSSA
Pinouts 121 100 80 64 64 MAP LQFP LQFP MAP LQFP BGA BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 K8 42 — — — PTA12 DISABLED PTA12 TPM1_CH0 FXIO0_D18 L8 43 — — — PTA13/ LLWU_P4 DISABLED PTA13/ LLWU_P4 TPM1_CH1 FXIO0_D19 K9 44 34 — — PTA14 DISABLED PTA14 SPI0_PCS0 LPUART0_ TX FXIO0_D20 L9 45 35 — — PTA15 DISABLED PTA15 SPI0_SCK LPUART0_ RX FXIO0_D21 J10 46 36 — — PTA16 DISABLED PTA16 SPI0_SOUT LPUART0_ CTS_b FXIO0_D22 H10 47 37 —
Pinouts 121 100 80 64 64 MAP LQFP LQFP MAP LQFP BGA BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 E7 61 — — — VDD VDD VDD B10 62 51 — — PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT LPUART0_ RX TPM_ CLKIN0 EWM_IN E9 63 52 — — PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN TPM_ CLKIN1 EWM_OUT_ b D9 64 53 D6 41 PTB18 TSI0_CH11 TSI0_CH11 PTB18 TPM2_CH0 FXIO0_D6 C9 65 54 C7 42 PTB19 TSI0_CH12 TSI0_CH12 PTB19 TPM2_CH1 FXIO0_D7 F10 66 — — —
Pinouts 121 100 80 64 64 MAP LQFP LQFP MAP LQFP BGA BGA Pin Name Default ALT0 ALT1 B5 87 — — — PTC15 DISABLED — 88 — — — VSS VSS VSS — 89 — — — VDD VDD VDD D5 — 71 — — PTC16 DISABLED PTC16 C4 90 72 — — PTC17 DISABLED PTC17 B4 — — — — PTC18 DISABLED PTC18 A4 — — — — PTC19 DISABLED PTC19 D4 91 73 C3 57 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 D3 92 74 A4 58 PTD1 C3 93 75 C2 59 B3 94 76 B3 A3 95 77 A2 96 B2 ALT2 ALT3 ALT4
Pinouts 121 100 80 64 64 MAP LQFP LQFP MAP LQFP BGA BGA 121 100 80 64 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 64 4.2 Pin properties 121 MAPBGA 100 LQFP 80 LQFP 64 LQFP 64 MAPBGA Pin Name Driver strength Default status after POR Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt The following table lists the pin properties.
Pin Name Driver strength Default status after POR Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt NC — — — — — — — 21 NC — — — — — — — K2 ADC0_DP0 ND Hi-Z — SS N N — K1 ADC0_DM0 ND Hi-Z — SS N N — 64 MAPBGA 20 64 LQFP 100 LQFP J2 80 LQFP 121 MAPBGA Pinouts F5 22 17 13 G2 VDDA — — — — — — — G5 23 18 14 H3 VREFH — — — — — — — G6 24 19 15 H2 VREFL — — — — — — —
Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt N Y N N Y Driver strength N SS Pin Name SS — 64 MAPBGA — Hi-Z 64 LQFP Hi-Z PTA11/LLWU_P23 ND 80 LQFP PTA10/LLWU_P22 ND H7 100 LQFP J9 121 MAPBGA Default status after POR Pinouts K8 42 PTA12 ND Hi-Z — SS N N Y L8 43 PTA13/LLWU_P4 ND Hi-Z — SS N N Y K9 44 34 PTA14 ND Hi-Z — SS N N Y L9 45 35 PTA15 ND Hi-Z — SS N N Y J10 46 36 PT
121 MAPBGA 100 LQFP 80 LQFP 64 LQFP 64 MAPBGA Pin Name Driver strength Default status after POR Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt Pinouts E9 63 52 PTB17 ND Hi-Z — SS N N Y D9 64 53 41 D6 PTB18 ND Hi-Z — SS N N Y C9 65 54 42 C7 PTB19 ND Hi-Z — SS N N Y F10 66 PTB20 ND Hi-Z — SS N N Y F9 67 PTB21 ND Hi-Z — SS N N Y F8 68 PTB22 ND Hi-Z — SS N N Y E8 69 PT
Driver strength Default status after POR Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt — SS N N Y Hi-Z — SS N N Y 64 MAPBGA Hi-Z ND 64 LQFP ND PTC19 80 LQFP PTC18 A4 100 LQFP B4 121 MAPBGA Pin Name Pinouts D4 91 73 57 C3 PTD0/LLWU_P12 ND Hi-Z — SS N N Y D3 92 74 58 A4 PTD1 ND Hi-Z — SS N N Y C3 93 75 59 C2 PTD2/LLWU_P13 ND Hi-Z — SS N N Y B3 94 76 60 B3 PTD3 ND Hi-Z —
Pinouts Properties Driver strength Default status after POR Abbreviation Descriptions ND Normal drive HD High drive Hi-Z High impendence H High level L Low level Pullup/ pulldown setting after POR PD Pullup PU Pulldown Slew rate after POR FS Fast slew rate SS Slow slew rate Passive Pin Filter after POR N Disabled Y Enabled Open drain N Disabled1 Y Enabled2 Y Yes Pin interrupt 1.
Pinouts 4.3.2 System modules Table 10. System signal descriptions Chip signal name Module signal name NMI_b — Description I/O Non-maskable interrupt I NOTE: Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin.
Pinouts Table 14. EMVSIM1 signal descriptions Chip signal name Module signal name EMVSIM1_CLK EMVSIM_SCLK Description I/O Card Clock. Clock to Smart Card. O I/O EMVSIM1_IO EMVSIM_IO Card Data Line. Bi-directional data line. EMVSIM1_PD EMVSIM_PD Card Presence Detect. Signal indicating presence or removal of card I EMVSIM1_RST EMVSIM_SRST Card Reset. Reset signal to Smart Card O EMVSIM1_VCCEN EMVSIM_VCC_EN Card Power Enable. This signal controls the power to Smart Card O 4.3.
Pinouts Table 17. QSPI signal description (continued) Chip signal name Module signal Name Description I/O second device in a dual-die package flash A or the second of the two flash devices that share IOFA. QSPI0B_SS0_B PCSFB1 Peripheral Chip Select Flash B1. This signal is the chip select for the serial flash device B1. B1 represents the first device in a dual-die package flash B or the first of the two flash devices that share IOFB. O QSPI0A_SCLK SCKFA Serial Clock Flash A.
Pinouts 4.3.5 Analog Table 18. ADC0 Signal Descriptions Chip signal name Module signal name Description I/O ADC0_DP[1:0] DADP1–DADP0 Differential analog channel inputs I ADC0_DM[1:0] DADM1–DADM0 Differential Analog Channel Inputs I Inputs1 ADC0_SEn ADn Single-Ended Analog Channel I VREFH VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog power supply I VSSA VSSA Analog ground I 1. See ADC channel assignment for the n.
Pinouts 4.3.6 Timer Modules Table 22. LPTMR0 Signal Descriptions Chip signal name Module signal name Description LPTMR0_ALT[2:1] LPTMR_ALTn Pulse Counter Input I/O I Table 23. LPTMR1 Signal Descriptions Chip signal name Module signal name Description LPTMR1_ALT[2:1] LPTMR_ALTn Pulse Counter Input I/O I Table 24. RTC Signal Descriptions Chip signal name Module signal name VBAT — EXTAL32 EXTAL32 XTAL32 XTAL32 Description I/O Backup battery supply for RTC and VBAT register file I 32.
Pinouts Table 27. TPM2 Signal Descriptions Chip signal name Module signal name Description I/O TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock. I TPM1_CH[1:0] TPM_CHn A TPM channel pin is configured as output when configured in an output compare or PWM mode and the TPM counter is enabled, otherwise the TPM channel pin is an input. I/O 4.3.7 Communication interfaces Table 28.
Pinouts Table 30. SPI1 signal descriptions Chip signal name Module signal name Description I/O SPI1_PCS0 PCS0/SS Peripheral Chip Select 0 (O) in the master mode and Slave Select (I) in the slave mode I/O SPI1_PCS[1:3] PCS[1:3] Peripheral Chip Selects 1–3 in the master mode O SPI1_SIN SIN Serial Data In I SPI1_SOUT SOUT Serial Data Out O SPI1_SCK SCK Serial Clock (O) in the master mode and Serial Clock (I) in the slave mode I/O Table 31.
Pinouts Table 34. LPUART1 signal descriptions (continued) Chip signal name Module signal name Description I/O LPUART1_TX LPUART_TX Transmit data. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or transmit direction is configured for receive data. I/O LPUART1_RX LPUART_RX Receive Data I Table 35.
Pinouts Table 38. EMVSIM1 signal descriptions (continued) Chip signal name Module signal name Description EMVSIM1_ PD EMVSIM_PD Card Presence Detect. Signal indicating presence or removal of card I EMVSIM1_ RST EMVSIM_SRST Card Reset. Reset signal to Smart Card O EMVSIM1_ VCCEN I/O EMVSIM_VCC_EN Card Power Enable. This signal controls the power to Smart Card O 4.3.8 Human-machine interfaces (HMI) Table 39.
Pinouts 1 2 3 4 5 6 7 8 9 10 11 A PTD7 PTD5 PTD4/ LLWU_P14 PTC19 PTC14 PTC13 PTC8 PTC4/ LLWU_P8 PTD9 PTD8/ LLWU_P24 NC A B PTE0 PTD6/ LLWU_P15 PTD3 PTC18 PTC15 PTC12 PTC7 PTC3/ LLWU_P7 PTC0 PTB16 PTB4 B C PTE2/ LLWU_P1 PTC17 PTC11/ LLWU_P11 PTC10 PTC6/ LLWU_P10 PTC2 PTB19 PTB11 PTB5 C D PTE4/ LLWU_P2 PTE3 PTD1 PTD0/ LLWU_P12 PTC16 PTC9 PTC5/ LLWU_P9 PTC1/ LLWU_P6 PTB18 PTB10 PTB8 D E PTE6/ LLWU_P16 PTE5 PTD11/ LLWU_P25 PTD10 VDDIO_E VDD VD
PTD1 PTD0/LLWU_P12 PTC17 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 92 91 90 89 88 87 86 85 84 83 82 81 80 PTC4/LLWU_P8 PTD2/LLWU_P13 PTC5/LLWU_P9 PTD3 94 93 76 PTD4/LLWU_P14 95 77 PTD5 96 PTC7 PTD6/LLWU_P15 97 PTC6/LLWU_P10 VSS 98 79 VDD 99 78 PTD7 100 Pinouts 75 VDD 2 74 VSS PTE2/LLWU_P1 3 73 PTC3/LLWU_P7 PTE3 4 72 PTC2 VSS 5 71 PTC1/LLWU_P6 PTC0 PTE0 1 PTE1/LLWU_P0 VDDIO_E 6 70 PTE4/LLWU_P2 7 69 PTB23 PTE5 8 68
PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC17 PTC16 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Pinouts PTE11 11 50 PTB11 VDDIO_E 12 49 PTB8 VSS 13 48 PTB7 USB0_DP 14 47 PTB6 USB0_DM 15 46 PTB5 USB_VDD 16 45 PTB4 VDDA 17 44 PTB1 VREFH 18 43 PTB0/LLWU_P5 VREFL 19 42 RESET_b VSSA 20 41 PTA19
Pinouts A B 1 2 3 4 5 6 PTE0 PTD7 PTD4/ LLWU_P14 PTD1 PTC11/ LLWU_P11 PTC8 PTD3 PTC10 PTC9 PTC7 VSS PTE2/ LLWU_P1 PTE1/ PTD6/ LLWU_P0 LLWU_P15 PTD2/ PTD0/ LLWU_P13 LLWU_P12 7 8 PTC6/ PTC5/ LLWU_P10 LLWU_P9 A PTC2 PTC4/ LLWU_P8 B PTC1/ LLWU_P6 PTB19 PTC3/ LLWU_P7 C C PTD5 D PTE5 PTE3 VDDIO_E PTA0 PTA1 PTB18 PTB8 PTC0 D E USB0_DP PTE4/ LLWU_P2 VSS VDD PTA2 PTB0/ LLWU_P5 PTB6 PTB7 E F USB0_DM USB_VDD VSS PTB5 PTB4 RESET_b F VREF_OUT/ RTC_WAK CMP0_I
PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinouts PTB18 VSS 9 40 PTB8 USB0_DP 10 39 PTB7 USB0_DM 11 38 PTB6 USB_VDD 12 37 PTB5 VDDA 13 36 PTB4 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 RESET_b VSSA 16 33 PTA19 ADC0_DP1 32 41 PTA18 8 31 PTE5 VSS PTB19 30 42 VDD 7 29 PTE4/LLWU_P2
Pinouts 4.5 Package dimensions The following figures show the dimensions of the package options for the devices supported by this document. Figure 10. 64-pin LQFP package dimensions 1 Kinetis KL82 Microcontroller, Rev.
Pinouts Figure 11. 64-pin LQFP package dimensions 2 58 NXP Semiconductors Kinetis KL82 Microcontroller, Rev.
Pinouts Figure 12. 64-pin MAPBGA package dimension Kinetis KL82 Microcontroller, Rev.
Pinouts Figure 13. 80-pin LQFP package dimension 1 60 NXP Semiconductors Kinetis KL82 Microcontroller, Rev.
Pinouts Figure 14. 80-pin LQFP package dimension 2 Kinetis KL82 Microcontroller, Rev.
Pinouts Figure 15. 100-pin LQFP package dimension 1 62 NXP Semiconductors Kinetis KL82 Microcontroller, Rev.
Pinouts Figure 16. 100-pin LQFP package dimension 2 Kinetis KL82 Microcontroller, Rev.
Electrical characteristics Figure 17. 121-pin MAPBGA package dimension 5 Electrical characteristics 64 NXP Semiconductors Kinetis KL82 Microcontroller, Rev.
Electrical characteristics 5.1 Terminology and guidelines 5.1.1 Definitions Key terms are defined in the following table: Term Rating Definition A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.
Electrical characteristics 5.1.2 Examples EX AM PL E Operating rating: EX AM PL E Operating requirement: EX AM PL E Operating behavior that includes a typical value: 5.1.3 Typical-value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 66 NXP Semiconductors Kinetis KL82 Microcontroller, Rev.
Electrical characteristics 5.1.4 Relationship between ratings and operating requirements .) ) ) ing rat e Op in. (m g tin ra in. t (m ax t (m n me rat e Op ing ire qu re ing rat e Op .
Electrical characteristics 5.2.2 Moisture handling ratings Symbol MSL Description Min. Max. Unit Notes — 3 — 1 Moisture sensitivity level 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.2.3 ESD handling ratings Symbol Description Min. Max.
Electrical characteristics 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5.3 General 5.3.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Input Signal High Low VIH 80% 50% 20% Midpoint1 VIL Fall Time Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 18.
Electrical characteristics Table 41. Voltage and current operating requirements (continued) Symbol Description Min. Max. Unit — 0.3 × VDD V 0.06 × VDD — V -25 — mA — +25 1.2 — V VPOR_VBAT — V • 2.7 V ≤ VDD ≤ 3.6 V Notes • 1.7 V ≤ VDD ≤ 2.
Electrical characteristics 1. Rising threshold is the sum of falling threshold and hysteresis voltage Table 43. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage 5.3.2.3 Symbol VOH IOHT Min. Typ. Max. Unit 0.8 1.1 1.5 V Voltage and current operating behaviors Table 44. Voltage and current operating behaviors Description Output high voltage — Standard IO Min. Max. Unit Not es 3.3 V, Iload = -5 mA VDD – 0.5 — V 1 1.71 V, Iload = -2.
Electrical characteristics 5.3.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSx –> RUN recovery times in the following table assume this clock configuration: • • • • CPU and system clocks = 72 MHz Bus clock = 24 MHz Flash clock = 24 MHz MCG mode=FEI Table 45. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.
Electrical characteristics Table 46. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) Unit -40 25 50 70 85 1051 IEREFSTEN4MHz External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 228 237 245 251 258 µA IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled.
Electrical characteristics Table 46. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) -40 25 50 70 Unit 85 1051 configured for low power mode using the internal clock and continuous conversions. 1. Only LQFP and MAPBGA packages support the data in this column. 5.3.2.
Electrical characteristics Table 47.
Electrical characteristics Table 47. Power consumption operating behaviors (continued) Symbol Description Typ. Max. Unit Notes IDD_WAIT Core disabled, system at 12 MHz, bus at 6 MHz, flash disabled (flash doze enabled), VDD = 3 V, all peripheral clocks disabled 25 °C 1.98 3.34 mA 5 IDD_VLPR Very Low Power Run Core Mark in Flash in Compute Operation mode: Core at 4 MHz, bus at 1 MHz, flash at 1 MHz, VDD = 3 V 25 °C 845 936.
Electrical characteristics Table 47. Power consumption operating behaviors (continued) Symbol Description IDD_VLPW Very Low Power Run Wait current, core disabled, system at 2 MHz, bus and flash at 0.5 MHz, all peripheral clocks disabled, VDD = 3 V IDD_VLPW IIDD_PSTOP2 IDD_STOP IDD_VLPS IDD_VLPS IDD_LLS3 IDD_LLS3 IDD_LLS3 Typ. Max. Unit Notes 25 °C 225 277.03 μA 6 Very Low Power Run Wait current, core disabled, system at 125 kHz, bus and flash at 31.
Electrical characteristics Table 47. Power consumption operating behaviors (continued) Symbol IDD_LLS2 IDD_LLS2 IDD_LLS2 IDD_VLLS3 IDD_VLLS3 IDD_VLLS3 Description Typ. Max. 70 °C 15.15 24.15 85 °C 21.88 40.52 105 °C 41.82 69.34 3.37 6.67 50 °C 6.82 13.42 70 °C 11.13 20.73 85 °C 16.84 31.46 105 °C 32.93 48.89 25 °C and below 4.49 7.79 50 °C 9.07 16.27 70 °C 12.98 22.58 85 °C 17.88 32.50 105 °C 35.98 51.94 25 °C and below 4.47 7.77 50 °C 8.79 15.
Electrical characteristics Table 47. Power consumption operating behaviors (continued) Symbol IDD_VLLS2 IDD_VLLS2 IDD_VLLS2 IDD_VLLS1 IDD_VLLS1 IDD_VLLS1 IDD_VLLS0 Description Typ. Max. Unit VLLS2 current, all peripheral disable, 25 °C and VDD = 3 V below 1.98 3.78 μA 50 °C 2.95 5.71 70 °C 4.83 9.33 85 °C 7.95 13.80 105 °C 16.92 24.26 25 °C and below 2.8 4.60 50 °C 3.74 6.50 70 °C 5.96 10.46 85 °C 9.35 15.20 105 °C 19.37 26.71 25 °C and below 2.56 4.36 50 °C 3.
Electrical characteristics Table 47. Power consumption operating behaviors (continued) Symbol IDD_VLLS0 IDD_VBAT IDD_VBAT IDD_VBAT IDD_VBAT Description VLLS0 current, all peripheral disabled, (SMC_STOPCTRL[PORPO] = 1), VDD = 3 V Average current with RTC and 32 kHz disabled at 3 V Average current with RTC and 32 kHz disabled at 1.8 V Average current when CPU is not accessing RTC register at 3.0 V including 32 kHz Average current when CPU is not accessing RTC register at 1.
Electrical characteristics 5.3.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFA Run Current Vs Core Frequency Temperature = 25, VDD = 3V 16.00E-03 14.00E-03 Current Consumption (A) 12.00E-03 Cache -- CG 10.00E-03 8.00E-03 ENABLE- ALLOFF ENABLE- ALLON 6.00E-03 4.00E-03 2.00E-03 000.
Electrical characteristics VLPR Current Vs Core Freq Temperature = 25, VDD= 3V 500.00E-06 450.00E-06 Current Consumption (A) 400.00E-06 350.00E-06 Cache -- CG 300.00E-06 250.00E-06 ALLOFF - ENABLE 200.00E-06 ALLON - ENABLE 150.00E-06 100.00E-06 50.00E-06 000.00E+00 1 2 4 1-1-1-1 1-2-2-2 1-4-4-4 -- Core Freq --Core:Bus:Flash:QSPI Figure 20. VLPR mode supply current vs. core frequency 5.3.2.
Electrical characteristics 5.3.2.7 EMC Radiated Emissions Web Search Procedure boilerplate To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.nxp.com. 2. Perform a keyword search for "EMC design" 5.3.2.8 Symbol Capacitance attributes Table 48. Capacitance attributes Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF 5.3.
Electrical characteristics 5.3.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, LPUART, timers, and I2C signals. Table 50. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.
Electrical characteristics 5.3.4.1 Thermal operating requirements Table 51. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C 64 MAPBGA Unit Notes 5.3.4.2 Thermal attributes Board type Symbol Descriptio n 121 MAPBGA 80 LQFP Single-layer (1s) RθJA Thermal resistance, junction to ambient (natural convection) 75.5 55 92.
Electrical characteristics Board type Symbol Descriptio n 121 MAPBGA 80 LQFP 64 MAPBGA Unit Notes outside center (natural convection) — RθJB_CSB Thermal 14.6 characterizati on parameter, junction to package top outside center (natural convection) — 19.5 °C/W 5 1.
Electrical characteristics 5.4.1.2 Symbol J1 SWD electricals Table 53. SWD full voltage range electricals Description Min. Max. Unit Operating voltage 1.71 3.
Electrical characteristics SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 22. Serial wire data timing 5.4.2 Clock modules 5.4.2.1 Symbol MCG specifications Table 54. MCG specifications Description Min. Typ. Max. Unit Notes fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C — 32.768 — kHz fints_t Internal reference frequency (slow clock) — user trimmed 31.25 — 39.
Electrical characteristics Table 54. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C — ± 0.
Electrical characteristics Table 54. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes 54.93 79.09 91.53 73.23 105.44 122.02 20 20.97 25 MHz 3, 4 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.
Electrical characteristics Table 54. MCG specifications (continued) Symbol Description Jcyc_pll PLL period jitter (RMS) Jacc_pll Dunl tpll_lock Min. Typ. Max. Unit Notes 9 • fvco = 180 MHz — 120 — ps • fvco = 360 MHz — 75 — ps PLL accumulated jitter over 1µs (RMS) 9 • fvco = 180 MHz — 1350 — ps • fvco = 360 MHz — 600 — ps ±4.47 — ±5.97 Lock exit frequency tolerance Lock detector detection time — 10-6 — 150 × + 1075(1/ fpll_ref) % s 10 1.
Electrical characteristics Table 55. IRC48M specifications (continued) Symbol Description Min. Typ. Max. Unit Notes 1 • Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) Δfirc48m_cl Closed loop total deviation of IRC48M frequency over voltage and temperature — — ± 0.1 %fhost Jcyc_irc48m Period Jitter (RMS) — 35 150 ps Startup time — 2 3 μs tirc48mst 2 1. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation.
Electrical characteristics Table 56. Oscillator DC electrical specifications (continued) Symbol RF RS Description Min. Typ. Max.
Electrical characteristics Table 57. Oscillator frequency specifications (continued) Symbol Description Min. Typ. Max.
Electrical characteristics 5.4.2.4.2 Symbol 32 kHz oscillator frequency specifications Table 59. 32 kHz oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal — 32.768 — kHz Crystal start-up time — 1000 — ms 1 fec_extal32 Externally provided input clock frequency — 32.768 — kHz 2 vec_extal32 Externally provided input clock amplitude 700 — VBAT mV 2, 3 fosc_lo tstart Description Notes 1.
Electrical characteristics 1 2 3 Clock Tck SFCK Tcss Tcsh CS Tis Tih Data in Figure 23. QuadSPI input timing (SDR mode) diagram • • • • • NOTE The below timing values are with default settings for sampling registers like QuadSPI_SMPR. A negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad. The below timing are for a load of 15pf (1.
Electrical characteristics 1 2 3 Clock Tck SFCK Tcss Tcsh CS Toh Tov Data out Figure 24. QuadSPI output timing (SDR mode) diagram Table 62. QuadSPI output timing (SDR mode) specifications Symbol Parameter Value Min Unit Max Tov Output Data Valid — 2.8 ns Toh Output Data Hold -1.
Electrical characteristics NOTE • Numbers are for a load of 15pf (1.8V) and 35pf (3V) • The numbers are for setting of hold condition in register QuadSPI_SMPR[DDRSNP] Table 63. QuadSPI input timing (DDR mode) specifications Symbol Parameter Value Min Tis Setup time for incoming data Tih Unit Max 4 (Without — learning) Hold time requirement for incoming data 1 1 (With learning) — 1.5 — ns ns 2 3 Clock Tck SFCK Tcss Tcsh CS Tov Toh Data out Figure 26.
Electrical characteristics RDS TsMIN ThMIN DI[7:0] Figure 27. QuadSPI input timing (Hyperflash mode) diagram Table 65. QuadSPI input timing (Hyperflash mode) specifications Symbol Parameter Value Min Unit Max TsMIN Setup time for incoming data 2 — ns ThMIN Hold time requirement for incoming data 2 — ns CK CK 2 Tclk SKMAX Tclk SKMIN THO TDVO Output Invalid Data Figure 28. QuadSPI output timing (Hyperflash mode) diagram Table 66.
Electrical characteristics Table 66. QuadSPI output timing (Hyperflash mode) specifications (continued) Symbol Parameter Value Min Unit Max Tho Output Data Hold 1.3 — ns TclkSKMAX Ck to Ck2 skew max — T/4 + 0.5 ns TclkSKMIN Ck to Ck2 skew min T/4 - 0.5 — ns NOTE Maximum clock frequency = 72 MHz. 5.4.3.2 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 5.4.3.2.
Electrical characteristics Table 68. Flash command timing specifications (continued) Symbol tvfykey Description Min. Typ. Max. Unit Notes — — 30 μs 1 Verify Backdoor Access Key execution time 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 5.4.3.2.3 Flash high voltage current behaviors Table 69. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 5.4.3.2.4 Symbol Min. Typ. Max.
Electrical characteristics All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 5.4.5.1.1 16-bit ADC operating conditions Table 71. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Absolute 1.71 — 3.6 V — ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.
Electrical characteristics 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 29.
Electrical characteristics Table 72. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description INL Integral non-linearity EFS Full-scale error EQ Quantization error ENOB Effective number of bits Conditions1 Min. Typ.2 Max. Unit Notes –2.7 to +1.9 LSB4 5 LSB4 VADIN = VDDA5 • 12-bit modes — ±1.0 • <12-bit modes — ±0.5 • 12-bit modes — –4 –5.4 • <12-bit modes — –1.4 –1.8 • 16-bit modes — –1 to 0 — • ≤13-bit modes — — ±0.5 –0.7 to +0.
Electrical characteristics 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5.
Electrical characteristics 5.4.5.2 CMP and 6-bit DAC electrical specifications Table 73. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA VAIN Analog input voltage VSS – 0.
Electrical characteristics 0.08 0.07 CMP Hystereris (V) 0.06 HYSTCTR Setting 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 32. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Kinetis KL82 Microcontroller, Rev.
Electrical characteristics 0.18 0.16 0.14 CMP Hysteresis (V) 0.12 HYSTCTR Setting 0.1 00 01 10 11 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 33. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 5.4.5.3 5.4.5.3.1 Symbol 12-bit DAC electrical characteristics 12-bit DAC operating requirements Table 74. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.6 V VDACR Reference voltage 1.13 3.
Electrical characteristics 5.4.5.3.2 Symbol 12-bit DAC operating behaviors Table 75. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.
Electrical characteristics 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 34. Typical INL error vs. digital code 110 NXP Semiconductors Kinetis KL82 Microcontroller, Rev.
Electrical characteristics 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 25 -40 55 85 105 125 Temperature °C Figure 35. Offset at half scale vs. temperature 5.4.5.4 Voltage reference electrical specifications Table 76. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device °C 100 nF Notes 1, 2 1.
Electrical characteristics Table 77. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V 1 Vout Voltage reference output — factory trim 1.1584 — 1.2376 V 1 Vout Voltage reference output — user trim 1.193 — 1.197 V 1 Vstep Voltage reference trim step — 0.
Electrical characteristics 5.4.7.1 EMV SIM specifications Each EMV SIM module interface consists of a total of five pins. The interface is designed to be used with synchronous Smart cards, meaning the EMV SIM module provides the clock used by the Smart card. The clock frequency is typically 372 times the Tx/Rx data rate; however, the EMV SIM module can also work with CLK frequencies of 16 times the Tx/Rx data rate. There is no timing relationship between the clock and the data.
Electrical characteristics The following table defines the general timing requirements for the EMV SIM interface. Table 80. Timing Specifications, High Drive Strength ID Parameter SI EMV SIM clock frequency 1 (EMVSIMn_CLK)1 Symbol Min Max Unit Sfreq 0.01 25 MHz SI EMV SIM clock rise time (EMVSIMn_CLK)2 2 Srise — 0.09 × (1/Sfreq) ns SI EMV SIM clock fall time (EMVSIMn_CLK)2 3 Sfall — 0.
Electrical characteristics EMVSIMn_VCCEN EMVSIMn_CLK EMVSIMn_IO RESPONSE 1 2 T0 Figure 37. Internal Reset Card Reset Sequence The following table defines the general timing requirements for the SIM interface. Table 81. Timing Specifications, Internal Reset Card Reset Sequence Ref Min Max Units 1 — 200 EMVSIMx_CLK clock cycles 2 400 40,000 EMVSIMx_CLK clock cycles 5.4.7.1.1.
Electrical characteristics EMVSIMn_VCCEN EMVSIMn_RST EMVSIMn_CLK RESPONSE EMVSIMn_IO 2 1 3 3 T0 T1 Figure 38. Active-Low-Reset Smart Card Reset Sequence The following table defines the general timing requirements for the EMVSIM interface.. Table 82. Timing Specifications, Internal Reset Card Reset Sequence 5.4.7.1.
Electrical characteristics SI10 EMVSIMn_PD EMVSIMn_RST SI7 EMVSIMn_CLK SI8 EMVSIMn_IO SI9 EMVSIMn_VCCEN Figure 39. Smart Card Interface Power Down AC Timing Table 83. Timing Requirements for Power-down Sequence Ref No Parameter Symbol Min Max Units SI7 EMVSIM reset to SIM clock stop Srst2clk 0.9 × 1/ Frtcclk 1.1 × 1/Frtcclk ns SI8 EMVSIM reset to SIM Tx data low Srst2dat 1.8 × 1/ Frtcclk 2.2 × 1/Frtcclk ns SI9 EMVSIM reset to SIM voltage enable low Srst2ven 2.7 × 1/ Frtcclk 3.
Electrical characteristics NOTE The MCGPLLCLK meets the USB jitter and signaling rate specifications for certification with the use of an external clock/crystal for both Device and Host modes. The IRC48M meets the USB jitter and signaling rate specifications for certification in Device mode when the USB clock recovery mode is enabled. It does not meet the USB signaling rate specifications for certification in Host mode operation. 5.4.7.
Electrical characteristics DSPI_PCSn DS3 DS4 DS8 DS7 (CPOL=0) DS1 DS2 DSPI_SCK DSPI_SIN Data First data DSPI_SOUT Last data DS5 DS6 First data Data Last data Figure 40. DSPI classic SPI timing — master mode Table 85. Slave mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.
Electrical characteristics 5.4.7.4 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 86.
Electrical characteristics Table 87. Slave mode DSPI timing (full voltage range) Num Description Min. Max. Unit 1.71 3.6 V — 7.5 MHz 8 x tBUS — ns Operating voltage Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS11 DSPI_SCK to DSPI_SOUT valid — 23.1 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2.6 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7.
Electrical characteristics Table 88. I2C timing (continued) Characteristic Symbol Standard Mode Minimum Data set-up time tSU; DAT Rise time of SDA and SCL signals tr Fall time of SDA and SCL signals tf 2505 — Fast Mode Maximum Minimum Maximum — 1003, 6 1000 Unit — ns 7 300 ns 6 20 +0.1Cb — 300 20 +0.1Cb 300 ns Set-up time for STOP condition tSU; STO 4 — 0.6 — µs Bus free time between STOP and START condition tBUF 4.7 — 1.
Electrical characteristics Table 89. I 2C 1Mbit/s timing (continued) Characteristic Symbol Minimum 1 Maximum Unit 120 ns Fall time of SDA and SCL signals tf 20 +0.1Cb Set-up time for STOP condition tSU; STO 0.26 — µs Bus free time between STOP and START condition tBUF 0.5 — µs Pulse width of spikes that must be suppressed by the input filter tSP 0 50 ns 1. Cb = total capacitance of the one bus line in pF.
Design considerations 6 Design considerations 6.1 Hardware design considerations This device contains protective circuitry to guard against damage due to high static voltage or electric fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. 6.1.1 Printed circuit board recommendations • Place connectors or cables on one edge of the board and do not place digital circuits between connectors.
Design considerations • Take special care to minimize noise levels on the VREFH/VREFL inputs. An option is to use the internal reference voltage (output 1.2 V typically) as the ADC reference. • VDDIO_E, which is dedicated to powering PORTE, must be powered after VDD and must be greater than or equal to VDD voltage. 6.1.3 Analog design Each ADC input must have an RC filter as shown in the following figure. The maximum value of R must be RAS max if fast sampling and high resolution are required.
OSCILLAT OSCILLATOR EXTAL Design considerations EXTAL XTAL 1 2 1 1 MCU CRYSTAL 2 R Cx ADCx 2 1 1 Analog input 2 CRYST C 2 6.1.4 Digital design OSCILLATOR Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V). EXTAL CAUTION 1 2 Do not provide power to I/O pins prior to VDD, especially the RF RESET_b pin. 1 RS 2 1 1 1 ADCx RF CRYSTAL Cx 2 1 The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor.
2 10k 4 Design considerations 3 OSCILLATOR Supervisor Chip EXTAL OSCILLATOR VDD EXTAL XTAL OSCILLATOR MCU XTAL EXTAL XTAL 1 MCU XTAL EXTAL 1 2 1 2 reset chip Figure 48. Reset signal connection to external RF RF RS XTAL 1 2 RF RS RS 2 Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low 1 2 2 1 level on this pin will trigger non-maskable interrupt.
1 2 C 2 2 2 1 1 R4 R3 BAT54SW Design considerations VDD 1 1 1 10k 2 SWD_DIO SWD_CLK RESET_b RESET_b RESET_b 0.1uF 1 2 0.1uF 2 4 6 8 10 1 1 3 5 7 9 C J1 2 10k VDD MCU VDD 2 HDR_5X2 2 10k Figure 50. SWD debug interface • Low leakage stop mode wakeup Supervisor Chip MCU 1 VDD OUT • Unused pin 0.1uF 2 Active high, open drain RS 1 2 Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the10k low leakage stop modes (LLS/VLLSx). See for pin selection.
Design considerations Table 91. External crystal/resonator connections Oscillator mode Oscillator mode Low frequency (32.768kHz), low power Diagram 1 Low4 frequency (32.768kHz), high gain Diagram 2, Diagram 4 High frequency (3-32MHz), low power Diagram 3 High frequency (3-32MHz), high gain Diagram 4 3 OSCILLATOR EXTAL EXTAL XTAL CRYSTAL ADCx CRYSTAL 1 Cy 2 CRYSTAL Cx Figure 51.
CRYSTAL 2 1 CRYSTAL Cy RESONATOR 2 2 Cx 3 2 1 1 2 1 1 Design considerations OSCILLATOR EXTAL XTAL 2 1 RF 1 RF 2 Cx CRYSTAL 2 2 1 3 1 CRYSTAL 2 RS Cy RESONATOR 2 1 1 2 2 RS 2 RS 1 XTAL 2 RF EXTAL 2 1 1 XTAL 1 EXTAL OSCILLATOR 1 OSCILLATOR Figure 54. Crystal connection – Diagram 4 6.
Part identification For all other partner-developed software and tools, visit http://www.nxp.com/partners. 6.3 Soldering temperature Base on JEDEC/IPC J-STD-020 Industry Standard, refer to AN3298: Solder Joint Temperature and Package Peak Temperature for soldering guideline of different packages. 7 Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.
Revision history Field Description Values • • • • MP = 64 MAPBGA (5 mm x 5 mm) LK = 80 LQFP (12 mm x 12 mm) LL = 100 LQFP (14 mm x 14 mm) MC = 121 MAPBGA (8 mm x 8 mm) CC Maximum CPU frequency (MHz) • 7 = 72 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 7.4 Example This is an example part number: MKL82Z128VMC7 8 Revision history The following table provides a revision history for this document. Table 92. Revision history Rev. No.
How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein.