Datasheet

Product Memory Core Package
Part Number Availability Flash SRAM Cortex-M4 Cortex-M0+ Package
K32L3A60VPJ1A Q3 2019 1.25 MB 384 kB √ √
176 VFBGA
9 x 9 x 0.86mm
0.5mm pitch
K32L3A60VLQ1A Q4 2019 1.25 MB 384 kB √ √
144 LQFP
20 x 20 x 1.6 mm
0.5mm pitch
K32L3B50VLL1A Q4 2020 1 MB 256 kB √
100 LQFP
14 x 14 x 1.7mm
0.5mm pitch
K32L3B50VMC1A Q4 2020 1 MB 256 kB √
121 MBGA
8 x 8 x 1.4mm
0.65 mm pitch
K32L3B40VLL1A Q4 2020 512 kB 128 kB √
100 LQFP
14 x 14 x 1.7mm
0.5mm pitch
K32L3B40VFW1A Q4 2020 512 kB 128 kB √
64 QFN
9 x 9 x 0.85 mm
0.5 mm pitch
ORDERABLE PART NUMBERS
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Document Number: K32MCUSFS REV 3
Features Benefits
Dual-Core Architecture
The dual-core feature (72 MHz Arm
®
Cortex
®
-M4 core and optional Cortex M0+ core) of this family makes it ideal for applications
that require a high-performance host process to run the application and a low-power processor for low-throughput operations
Large On-Chip Memory
Ample memory resources (with up to 1.25 MB flash, up to 384 kB SRAM and 48 kB ROM (Bootloader)) to fit different custom
application code and data, reducing complex two-chip solutions to a single device
High Security
• Resource Domain Controller for access control, system memory protection and peripheral isolation
• Cryptographic subsystem that includes a dedicated core, dedicated instruction memory (IRAM and IROM) and dedicated data
RAM for autonomous implementation of encryption, signing, and hashing algorithms including AES, DES, SHA, RSA and ECC
• Secure key management for storing and protecting sensitive security keys
• Wiping of the crypto subsystem memory, including security keys, upon sensing a security breach or physical tamper event
Secure Boot Built-in secure boot to assure only authorized and authenticated code runs in the device
DC-DC Converter Reduces the effective current consumption over standard bypass mode
Analog High-performance on-chip analog (ADC, DAC, CMP) for sensor aggregation and other sophisticated applications
Small, High Pin-Count Packages Large I/O capability in different packages including BGA, LQFP and QFN
Comprehensive Enablement Complete development hardware, software stacks, drivers and RTOS for easy design and fast time-to-market
K32 L3 MCU FAMILY KEY FEATURES AND BENEFITS
K32 L3 SERIES OVERVIEW
LP ADC
(12-bit)
Arm
®
Cortex
®
-M4
Up to 72 MHz
External Watchdog
LPIT 2x
(4 Channel)
FLASH
Up to 1.25 MB
Core Platform
System Control
Watchdog
Timers
Memory
RAM
Up to 384 kB
Boot ROM
48 kB
Communication and HMI Interfaces
EMVSIM External Bus
Analog
Security
Clocks
Arm Cortex-M0+
Up to 72 MHz
System PWR Management Low-Leakage Wake-Up
System CLK Generator Peripheral CLK CTRL
DMA
Trigger Multiplexer
Random NUM Generator
CAU Tamper
CRC
Resource Domain CTRL
LPTMR 3x
(32-bit)
TPM 2x
(6 Channel)
TPM 2x
(2 Channel)
Time Stamp Timer Real-Time Clock
FlexIO GPIO
LP I
2
C 4x
SAI
SDHC LP SPI 4x
LP UART 4x USB
LP DAC
(12-bit)
Battery Monitor
Temperature Sensor
RTC OSC
32.768 kHz
FIRC
48/52/56/60 MHz
SIRC
2/8 MHz
LP FLL
48/72 MHz
Optional
DSP, sFPU, NVIC, SysTick
Division, Square Root, NVIC, Systick
LP CMP 2x
Dual Output DC/DC
K32 L3 MCU FAMILY BLOCK DIAGRAM