Datasheet

MMA8652FC
Sensors
Freescale Semiconductor, Inc. 51
6.11 Auto-WAKE/SLEEP detection
6.11.1 0x29: ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write)
The ASLP_COUNT register sets the minimum time period of inactivity required to switch the part between Wake and Sleep
status. At the end of the time period, the device switches its ODR rate automatically when the Auto-WAKE /SLEEP function is
enabled.
• Wake ODR is set by CTRL_REG1[DR] bits.
• Sleep ODR is set by CTRL_REG1[ASLP_RATE] bits.
• Auto WAKE/SLEEP function is enabled by asserting the CTRL_REG2[SLPE] bit.
D7–D0 defines the minimum duration time needed to change the current ODR value from DR to ASLP_RATE. The time step and
maximum value depend on the ODR chosen (as shown in Table 91).
For functional blocks that may be monitored for inactivity (to trigger the “return to SLEEP” event), see Table 92.
Table 89.
0x29 ASLP_COUNT register (Read/Write)
Back to Register Address Map
Bit
7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
Table 90. ASLP_COUNT register
Bit(s) Field Description
7–0 D[7:0]
Duration value
0000_0000 (default)
Table 91. ASLP_COUNT relationship with ODR
Output Data Rate
(ODR)
Duration
(sec)
ODR Time Step
(ms)
ASLP_COUNT Step
(ms)
800 Hz 0 to 81 1.25 320
400 Hz 0 to 81 2.5 320
200 Hz 0 to 81 5 320
100 Hz 0 to 81 10 320
50 Hz 0 to 81 20 320
12.5 Hz 0 to 81 80 320
6.25 Hz 0 to 81 160 320
1.56 Hz 0 to 162 640 640
Table 92. SLEEP/WAKE mode gates and triggers
Interrupt Source
Will the event restart the timer
and delay “Return to SLEEP”?
Will the event
WAKE from SLEEP?
Notes
FIFO_GATE Yes No
* If the FIFO_GATE bit is set to 1, then the assertion of the
SRC_ASLP interrupt does not prevent the system from
transitioning to SLEEP or from WAKE mode; instead the
assertion of the interrupt prevents the FIFO buffer from
accepting new sample data—until the host application
flushes the FIFO buffer.
SRC_TRANS Yes Yes
SRC_LNDPRT Yes Yes
SRC_PULSE Yes Yes
SRC_FF_MT Yes Yes
SRC_ASLP No* No*
SRC_DRDY No No