Datasheet
MMA8652FC
Sensors
40 Freescale Semiconductor, Inc.
6.8.4 0x17: FF_MT_THS Freefall and Motion Threshold register
FF_MT_THS is the threshold register used to detect freefall motion events.
• The unsigned 7-bit FF_MT_THS threshold register holds the threshold for the freefall detection where the magnitude of
the X and Y and Z acceleration values is lower or equal than
the threshold value.
• Conversely, the FF_MT_THS also holds the threshold for the motion detection where the magnitude of the X or Y or Z
acceleration value is higher than the threshold value.
The threshold resolution is 0.063 g/LSB and the threshold register has a range of 0 to 127 counts. The maximum range is to ±8 g.
Note that even when the full scale value is set to ±2 g or ±4 g, the motion still detects up to ±8 g.
The DBCNTM bit configures the way in which the debounce counter is reset when the inertial event of interest is momentarily not
true.
• When the DBCNTM bit is 1, the debounce counter is cleared to 0 whenever the inertial event of interest is no longer true
as shown in Figure 15, (b).
• While the DBCNTM bit is set to 0, the debounce counter is decremented by 1 whenever the inertial event of interest is no
longer true (Figure 15, (c)) until the debounce counter reaches 0 or until the inertial event of interest becomes active.
Decrementing the debounce counter acts as a median enabling the system to filter out irregular spurious events (which might
impede the detection of inertial events).
6.8.5 0x18 FF_MT_COUNT Debounce register
The Debounce register sets the number of debounce sample counts for the event trigger.
The Debounce register sets the minimum number of debounce sample counts that continuously match the detection condition
selected by you for the freefall/motion event.
When the internal debounce counter reaches the FF_MT_COUNT value, a freefall/motion event flag is set. The debounce
counter will never increase beyond the FF_MT_COUNT value. The time step used for the debounce sample count depends on
the ODR chosen and the Oversampling mode, as shown in Table 57.
Table 53.
0x17 FF_MT_THS register (Read/Write)
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Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 54.
FF_MT_THS
register
Bit(s) Field Description
7DBCNTM
Debounce counter mode selection
0 Increments or decrements debounce (default)
1 Increments or clears counter.
6–0 THS[6:0]
Freefall /Motion Threshold
000_0000 (default)
Table 55.
0x18 FF_MT_COUNT register (Read/Write)
Back to Register Address Map
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
D7 D6 D5 D4 D3 D2 D1 D0
Table 56. FF_MT_COUNT register
Bit(s) Field Description
7–0 D[7:0]
Count value
0000_0000 (default)