Datasheet

MMA8652FC
Sensors
Freescale Semiconductor, Inc. 29
6.5 System status and ID registers
6.5.1 0x0B: SYSMOD System Mode register
The System mode register indicates the current device operating mode. Applications using the Auto-SLEEP/WAKE mechanism
should use the SYSMOD register to synchronize the application with the device operating mode transitions. The SYSMOD register
also indicates:
• the status of the FIFO gate error
• and the number of samples since the gate error occurred.
6.5.2 0x0C: INT_SOURCE System Interrupt Status register
In the interrupt source register, the status of the various embedded features can be determined.
• The bits that are set (logic ‘1’) indicate which function has asserted an interrupt.
• The bits that are cleared (logic ‘0’) indicate which function has not asserted (or has deasserted) an interrupt.
INT_SOURCE register bits are set by a low-to-high transition, and are cleared by reading the appropriate interrupt source register.
For example, the SRC_DRDY bit is cleared when the ZYXDR bit (STATUS register) is cleared, but the SRC_DRDY bit is not
cleared by simply reading the STATUS register (0x00), but is cleared by reading all the X, Y, and Z MSB data.
Table 23. 0x0B SYSMOD: System Mode register (Read-Only)
Back to Register Address Map
Bit
7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FGERR FGT_4 FGT_3 FGT_2 FGT_1 FGT_0 SYSMOD1 SYSMOD0
Table 24. SYSMOD register
Bit(s) Field Description
7FGERR
FIFO Gate Error
0 No FIFO Gate Error detected. (default)
1 FIFO Gate Error was detected.
Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register.
For more information about configuring the FIFO Gate function, see Section 6.12.3, “0x2C: CTRL_REG3
Interrupt Control register”.
6–2 FGT[4:0]
Number of ODR time units since FGERR was asserted.
Reset when FGERR bit is cleared.
0_0000 (default)
1–0 SYSMOD[1:0]
System Mode
00 STANDBY mode (default)
01 WAKE mode
10 SLEEP mode
Table 25. 0x0C INT_SOURCE: System Interrupt Status register (Read Only) Back to Register Address Map
Bit
7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SRC_ASLP SRC_FIFO SRC_TRANS SRC_LNDPRT SRC_PULSE SRC_FF_MT — SRC_DRDY