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improvements in the design of its products.

Freescale Semiconductor Document Number: MMA8652FC

Data Sheet: Technical Data Rev. 3.3, 10/2015

An Energy-Efficient Solution by Freescale

MA8652FC, 3-Axis, 12-bit, Digital

Accelerometer

The MMA8652FC is an intelligent, low-power, three-axis, capacitive micromachined

accelerometer with 12 bits of resolution. This accelerometer is packed with

embedded functions with flexible user-programmable options, configurable to two

interrupt pins. Embedded interrupt functions enable overall power savings, by

relieving the host processor from continuously polling data. There is access to

either low-pass or high-pass filtered data, which minimizes the data analysis

required for jolt detection and faster transitions. The device can be configured to

generate inertial wake-up interrupt signals from any combination of the

configurable embedded functions, enabling the MMA8652FC to monitor inertial

events while remaining in a low-power mode during periods of inactivity. The

MMA8652FC is available in a small 10-pin DFN package (2 mm x 2 mm x 1 mm).

Features

• 1.95 V to 3.6 V supply voltage

• 1.62 V to 3.6 V digital interface voltage

• ±2 g, ±4 g, and ±8 g dynamically selectable full-scale ranges

• Output Data Rates (ODR) from 1.56 Hz to 800 Hz

• 12-bit digital output

•I

digital output interface with programmable interrupts

• Four embedded channels of configurable motion detection (Freefall, Motion,

Pulse, Transient)

• Orientation (Portrait/Landscape) detection with programmable hysteresis

• Configurable automatic ODR change triggered by the Auto-Wake/Sleep

state change

• 32-sample FIFO

• High-Pass Filter Data available per sample and through the FIFO

•Self-Test

Typical applications

• Tilt compensation in e-compass applications

• Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/

ront position identification)

• Notebook, tablet, e-reader, and laptop tumble and freefall detection

• Real-time orientation detection (virtual reality and gaming 3D user orientation feedback)

• Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup)

• Motion detection for portable product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming)

• Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)

•

User interface (tilt menu scrolling, tap detection for button replacement

)

ORDERING INFORMATION

Part Number Temperature Range Package Description Shipping

MMA8652FCR1 -40°C to +85°C DFN-10 Tape and Reel

MMA8652FC

Top View

Pin Connections

VDD

SCL

INT1

BYP

INT2

SDA

GND

VDDIO

GND

10-pin DFN

2 mm x 2 mm x 1 mm

Case 98ASA00301D

Top and Bottom View

Summary of content (65 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data Document Number: MMA8652FC Rev. 3.3, 10/2015 An Energy-Efficient Solution by Freescale MMA8652FC, 3-Axis, 12-bit, Digital MMA8652FC Accelerometer The MMA8652FC is an intelligent, low-power, three-axis, capacitive micromachined accelerometer with 12 bits of resolution. This accelerometer is packed with embedded functions with flexible user-programmable options, configurable to two interrupt pins.
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Table 1.
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Contents 1 Block Diagram and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MMA8652FC 4 Sensors Freescale Semiconductor, Inc.
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1 Block Diagram and Pin Descriptions 1.1 Block diagram BYP VDD VDDIO Voltage Regulator Clock GEN Internal OSC INT1 INT2 GND Y-axis Transducer MUX X-axis Transducer C-to-V Converter AAF Embedded Functions ADC I2 C Interface SDA SCL Anti-Aliasing Filter Z-axis Transducer 32 Data Point Configurable FIFO Buffer with Watermark Gain Freefall and Motion Detection Transient Detection (i.e.
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1.2 Pin descriptions SDA 10 1 VDD GND SCL VDDIO INT1 GND BYP GND 6 5 INT2 Figure 2. Pin connections (bottom view) Table 1. Pin descriptions Pin # Pin Name 1 VDD 2 Description Notes Power supply Device power is supplied through the VDD line. Power supply decoupling capacitors should be placed as close as possible to pin 1 and pin 8 of the device. SCL(1) I2C Serial Clock 7-bit I2C device address is 0x1D.
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2 Mechanical and Electrical Specifications 2.1 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 2. Maximum ratings Rating Symbol Value Unit Maximum acceleration (all axes, 100 μs) gmax 10,000 g Supply voltage VDD –0.3 to +3.6 V Vin –0.3 to VDDIO + 0.3 V Ddrop 1.
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2.2 Mechanical characteristics Table 4. Mechanical characteristics at VDD = 2.5 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted Parameter Full-Scale measurement range Sensitivity Symbol FS So Test Conditions Min Typ Max Unit FS[1:0] set to 00 ±2 g mode ±2 FS[1:0] set to 01 ±4 g mode ±4 FS[1:0] set to 10 ±8 g mode ±8 FS[1:0] set to 00 ±2 g mode 1024 FS[1:0] set to 01 ±4 g mode 512 FS[1:0] set to 10 ±8 g mode 256 ±2.5 % –40°C to 85°C ±0.
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2.3 Electrical characteristics Table 5. Electrical characteristics at VDD = 2.5 V, VDDIO = 1.8 V, T = 25°C, unless otherwise noted Parameter Supply voltage Interface supply voltage Low Power mode Normal mode Boot-Up current Value of capacitor on BYP pin Symbol Test Conditions VDD VDDIO IddLP Idd Min Typ Max Unit 1.95 2.5 3.6 V 1.62 1.8 3.6 V ODR = 1.563 Hz 6.5 ODR = 6.25 Hz 6.5 ODR = 12.5 Hz 6.
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2.4 I2C interface characteristic Table 6. I2C slave timing values (1) Parameter Symbol I2C Fast Mode Min Max 400 Unit SCL clock frequency fSCL 0 Bus-free time between STOP and START condition tBUF 1.3 μs (Repeated) START hold time tHD;STA 0.6 μs Repeated START setup time tSU;STA 0.6 μs STOP condition setup time tSU;STO 0.6 kHz μs μs SDA data hold time tHD;DAT 0.05 SDA setup time tSU;DAT 100 ns SCL clock low time tLOW 1.3 μs SCL clock high time tHIGH 0.
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3 Terminology 3.1 Sensitivity The sensitivity is represented in counts/g. • In ±2 g mode, sensitivity = 1024counts/g. • In ±4 g mode, sensitivity = 512counts/g. • In ±8 g mode, sensitivity = 256counts/g. 3.2 Zero-g offset Zero-g Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A sensor stationary on a horizontal surface will measure 0 g in X-axis and 0 g in Y-axis, whereas the Z-axis will measure 1 g.
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4 Modes of Operation ACTIVE SLEEP OFF STANDBY WAKE Figure 5. Operating modes for MMA8652FC Table 7. Operating modes Mode OFF I2C Bus State Powered down VDD VDDIO Description <1.8 V VDDIO can be > VDD • The device is powered off. • All analog and digital blocks are shutdown. • I2C bus inhibited. STANDBY I2C communication with MMA8652FC is possible ON VDDIO = High VDD = High ACTIVE bit is cleared • Only digital blocks are enabled. • Analog subsystem is disabled. • Internal clocks disabled.
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5 Functionality The MMA8652FC is a low-power, digital output 3-axis linear accelerometer with a I2C interface with embedded logic used to detect events and notify an external microprocessor over interrupt lines. • 8-bit or 12-bit data, high-pass filtered data, 8-bit or 12-bit configurable 32-sample FIFO • Four different oversampling options that allow for the optimum resolution vs.
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Table 8. Accelerometer 12-bit output data (Continued) 12-bit data Range ±2 g (1 mg/LSB) Range ±4 g (2 mg/LSB) Range ±8 g (4 mg/LSB) … … … … 1000 0000 0001 –1.999 g –3.998 g –7.996 g 1000 0000 0000 –2.0000 g –4.0000 g –8.0000 g Range ±4 g (31.25 mg/LSB) Range ±8 g (62.5 mg/LSB) Table 9. Accelerometer 8-bit output data 8-bit Data 5.3 Range ±2 g (15.6 mg/LSB) 0111 1111 1.9844 g +3.9688 g +7.9375 g 0111 1110 1.9688 g +3.9375 g +7.8750 g … … … … 0000 0001 +0.0156 g +0.
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5.5 Auto-WAKE/SLEEP mode The MMA8652FC can be configured to transition between sample rates (with their respective current consumption) based on four of the interrupt functions of the device. The advantage of using the Auto-WAKE/SLEEP is that the system can automatically transition to a higher sample rate (higher current consumption) when needed, but spends the majority of the time in the SLEEP mode (lower current) when the device does not require higher sampling rates.
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The Transient Detection function can be routed to either interrupt pin through bit 5 in CTRL_REG5 register (0x2E). Registers 0x1D – 0x20 are the dedicated Transient Detection configuration registers. The source register contains directional data to determine the direction of the acceleration (either positive or negative). 5.8 Tap detection The MMA8652FC has embedded single/double and directional tap detection.
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PORTRAIT 90° PORTRAIT 90° Landscape-to-Portrait Trip Angle = Midpoint + hysterisis value Portrait-to-Landscape Trip Angle = midpoint - hysteresis value 0° Landscape 0° Landscape Figure 7. Landscape-to-Portrait transition trip angles The MMA8652FC orientation detection algorithm confirms the reliability of the function with a configurable Z-lockout angle.
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5.10 Interrupt register configurations There are seven configurable interrupts in the MMA8652FC: Data Ready, Motion/Freefall, Tap (Pulse), Orientation, Transient, FIFO events, and Auto-SLEEP events. Configurable interrupts These seven interrupt sources can be routed to one of two interrupt pins. Data Ready The interrupt source must be enabled and configured.
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4. 5. 6. The 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low, so that it remains stable low during the high period of the acknowledge clock period. A Master may also issue a repeated START during a data transfer. The MMA8652FC expects repeated STARTs to be used to randomly read from specific registers.
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Master ST Device Address[7:1] W Register Address[7:0] AK Slave AK Master Data[7:0] Slave SR Device Address[7:1] R AK AK Data[7:0] AK AK Data[7:0] NAK SP Data[7:0] Figure 11. Multiple Byte Read timing (I2C) 5.11.3 1. 2. 3. 4. Master Single byte write To start a write command, the Master transmits a start condition (ST) to the MMA8652FC, slave address ($1D) with the R/W bit set to “0” for a write, The MMA8652FC sends an acknowledgement.
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6 Register Descriptions 6.1 Register address map Table 12. MMA8652FC register address map Auto-Increment Address Register Type Address FMODE = 0 FMODE > 0 FMODE = 0 FMODE > 0 Name Default Hex Value 00000000 0x00 Output — [7:0] are 8 MSBs of 12-bit sample.
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Table 12.
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6.2 Register bit map Table 13.
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Table 13.
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6.3 Data registers The following are the data registers for the MMA8652FC device. For more information about data manipulation in the MMA8652FC, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. • When the F_MODE bits (F_SETUP register 0x09, bit 6 and 7) are cleared, the FIFO is not ON. Register 0x00 reflects the real-time status information of the X, Y and Z sample data.
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• • The LSB registers can only be read immediately following the read access of the corresponding MSB register. — A random read access to the LSB registers is not possible. — Reading the MSB register and then the LSB register in sequence ensures that both bytes (LSB and MSB) belong to the same data sample, even if a new data sample arrives between reading the MSB and the LSB byte.
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6.4 FIFO registers The following registers are used to configure the FIFO. For more information about the FIFO, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. 6.4.1 0x00: F_STATUS FIFO Status register (F_MODE > 0) When F_MODE > 0, Register 0x00 becomes the FIFO Status Register, which is used to retrieve information about the FIFO.
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Table 20. F_SETUP register Bit(s) 7–6 Field Description F_MODE[1:0](1)(2) FIFO buffer overflow mode 00 FIFO is disabled. (default) 01 FIFO contains the most recent samples when overflowed (circular buffer). The oldest sample is discarded and replaced by a new sample. 10 FIFO stops accepting new samples when overflowed. 11 Trigger mode. The FIFO will be in a circular mode up to the number of samples in the watermark.
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6.5 System status and ID registers 6.5.1 0x0B: SYSMOD System Mode register The System mode register indicates the current device operating mode. Applications using the Auto-SLEEP/WAKE mechanism should use the SYSMOD register to synchronize the application with the device operating mode transitions. The SYSMOD register also indicates: • the status of the FIFO gate error • and the number of samples since the gate error occurred. Table 23.
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Table 26. INT_SOURCE register Bit(s) Field Description SRC_ASLP Auto-SLEEP/WAKE interrupt status bit • WAKE-to-SLEEP transition occurs when no interrupt occurs for a time period that exceeds the userspecified limit (ASLP_COUNT). This causes the system to transition to a user-specified low ODR setting. • SLEEP-to-WAKE transition occurs when the user-specified interrupt event has woken the system; thus causing the system to transition to a user-specified high ODR setting.
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6.6 Data configuration registers 6.6.1 0x0E: XYZ_DATA_CFG register The XYZ_DATA_CFG register sets the dynamic range and sets the high-pass filter for the output data. When the HPF_OUT bit is set, the FIFO and DATA registers both will contain high-pass filtered data. Table 28. 0x0E: XYZ_DATA_CFG register (Read/Write) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 HPF_OUT Back to Register Address Map Bit 3 0 Bit 2 0 Bit 1 FS1 Bit 0 FS0 Table 29.
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6.6.2 0x0F: HP_FILTER_CUTOFF High-Pass Filter register The High-Pass Filter register sets the high-pass filter cutoff frequency for removal of the offset and slower changing acceleration data. The output of this filter is logged in the data registers (0x01–0x06) when bit 4 (HPF_OUT) of Register 0x0E is set. The filter cutoff options change based on the data rate selected, as shown in Table 33.
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6.7 Portrait/Landscape configuration and status registers For more information about the different user-configurable settings and example code, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. 6.7.1 0x10: PL_STATUS Portrait/Landscape Status register To get updated information on any change in orientation, read the Portrait/Landscape Status register (read Bit 7, or read the other bits for more orientation data).
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6.7.2 0x11 Portrait/Landscape Configuration register The Portrait/Landscape Configuration register enables the portrait/landscape function and sets the behavior of the debounce counter. Table 36. 0x11 PL_CFG register (Read/Write) Bit 7 DBCNTM Bit 6 PL_EN Back to Register Address Map Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 — Bit 0 — Table 37. PL_CFG register Bit(s) Field 7 DBCNTM 6 PL_EN 5–0 — 6.7.
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6.7.4 0x13: PL_BF_ZCOMP Back/Front and Z Compensation register The Z-Lock angle compensation bits allows you to adjust the Z-lockout region from 14° up to 43°. On power-up, the default Z-lockout angle is set to the default value of 29°. The back-to-front trip angle is set by default to ±75°, and this angle can be adjusted from a range of 65° to 80° (with 5° step increments). Table 41.
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Table 46. P_L_THS_REG register (Continued) 7–3 2–0 Portrait/Landscape trip threshold angle (from 15° to 75°) See Table 47, “Threshold angle thresholds look-up table,” on P_L_THS[7:3] page 36 for the values with the corresponding approximate threshold For the landscape/portrait detection to work angle. correctly, 1_0000 (45°) (default) THS + HYS > 0 Hysteresis value and THS + HYS < 32. This angle is added to the threshold angle, for a smoother transition All angles are accurate to ±2°.
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6.8 Freefall/Motion configuration and status registers The freefall/motion function can be configured in either Freefall or Motion Detection mode via the OAE configuration bit (0x15: FF_MTG_CFG, bit 6). The freefall/motion detection block can be disabled by setting all three bits (ZEFE, YEFE, XEFE) to zero. Depending on the register bits ELE (0x15: FF_MTG_CFG, bit 7) and OAE (0x15: FF_MTG_CFG, bit 6), each of the freefall and motion detection block can operate in four different modes. 6.8.1 6.8.1.
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6.8.2 0x15: FF_MT_CFG Freefall/Motion Configuration register This is the Freefall/Motion configuration register for setting up the conditions of the freefall or motion function. Table 49. 0x15 FF_MT_CFG register (Read/Write) Bit 7 ELE Bit 6 OAE Bit 5 ZEFE Back to Register Address Map Bit 4 YEFE Bit 3 XEFE Bit 2 — Bit 1 — Bit 0 — Table 50. FF_MT_CFG register Bit(s) Field Description ELE Event Latch Enable: Event flags are latched into FF_MT_SRC register.
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6.8.3 0x16: FF_MT_SRC Freefall/Motion Source register The Freefall/Motion Source register keeps track of the acceleration event that is triggering (or has triggered, if ELE bit in FF_MT_CFG register is set to 1) the event flag. In particular, EA is set to 1 when the logical combination of acceleration events flags specified in FF_MT_CFG register is true. This EA bit is used in combination with the values in INT_EN_FF_MT and INT_CFG_FF_MT register bits to generate the freefall/motion interrupts.
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6.8.4 0x17: FF_MT_THS Freefall and Motion Threshold register FF_MT_THS is the threshold register used to detect freefall motion events. • The unsigned 7-bit FF_MT_THS threshold register holds the threshold for the freefall detection where the magnitude of the X and Y and Z acceleration values is lower or equal than the threshold value.
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Table 57. FF_MT_COUNT relationship with the ODR Max Time Range (s) Time Step (ms) ODR (Hz) Normal LPLN HighRes LP Normal LPLN HighRes LP 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 20.4 0.638 40.8 20 80 2.5 160 1.56 5.1 20.4 0.
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6.9 Transient configuration and status registers For more information about the uses of the transient function, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. This Transient (HPF) acceleration detection function is similar to the motion detection function, except that high-pass filtered data is compared. There is an option to disable the high-pass filter through the function. In this case, the behavior is the same as the motion detection.
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6.9.2 0x1E TRANSIENT_SRC register The transient source register provides the status of the enabled axes and the polarity (directional) information. When the TRANSIENT_SRC register is read, it clears the interrupt for the transient detection. When new events arrive while EA = 1, additional *TRANSE bits may get set, and the corresponding *_Trans_Pol flag become updated. However no *TRANSE bit may get cleared before the TRANSIENT_SRC register is read. Table 60.
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6.9.3 0x1F TRANSIENT_THS register The Transient Threshold register sets the threshold limit for the detection of the transient acceleration. The value in the TRANSIENT_THS register corresponds to a g value, which is compared against the values of high-pass filtered data. If the highpass filtered acceleration value exceeds the threshold limit, an event flag is raised and the interrupt is generated (if enabled). Table 62.
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6.10 Pulse configuration and status registers For more information about of how to configure the tap detection and sample code, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. The tap detection registers are referred to as “Pulse”. 6.10.1 0x21: PULSE_CFG Pulse Configuration register The PULSE_CFG register configures the event flag for tap detection, enabling/disabling the detection of a single and double pulse on each of the axes. Table 67.
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6.10.2 0x22: PULSE_SRC Pulse Source register The PULSE_SRC register indicates a double or single pulse event has occurred (and also which direction). The corresponding axis and event must be enabled in register 0x21 for the event flag to be asserted in the source register. Table 69. 0x22 PULSE_SRC register (Read-Only) Bit 7 EA Bit 6 AxZ Bit 5 AxY Back to Register Address Map Bit 4 AxX Bit 3 DPE Bit 2 PolZ Bit 1 PolY Bit 0 PolX Table 70.
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6.10.3 0x23 – 0x25: PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers The pulse threshold can be set separately for the X, Y, and Z axes. The PULSE_THSX, PULSE_THSY and PULSE_THSZ registers define the threshold that is used by the system to start the pulse detection procedure. Table 71. 0x23 PULSE_THSX register (Read/Write) Bit 7 0 Bit 6 THSX6 Bit 5 THSX5 Bit 4 THSX4 Back to Register Address Map Bit 3 THSX3 Bit 2 THSX2 Bit 1 THSX1 Bit 0 THSX0 Table 72.
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6.10.4 0x26: PULSE_TMLT Pulse Time Window 1 register Table 77. 0x26 PULSE_TMLT register (Read/Write) Bit 7 TMLT7 Bit 6 TMLT6 Bit 5 TMLT5 Back to Register Address Map Bit 4 TMLT4 Bit 3 TMLT3 Bit 2 TMLT2 Bit 1 TMLT1 Bit 0 TMLT0 Table 78.
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6.10.5 0x27: PULSE_LTCY Pulse Latency Timer register Table 81. 0x27 PULSE_LTCY register (Read/Write) Bit 7 LTCY7 Bit 6 LTCY6 Bit 5 LTCY5 Back to Register Address Map Bit 4 LTCY4 Bit 3 LTCY3 Bit 2 LTCY2 Bit 1 LTCY1 Bit 0 LTCY0 Table 82. PULSE_LTCY register Bit(s) Field 7–0 Description Latency Time Limit 0000_0000 (default) LTCY[7:0] Bits LTCY7 – LTCY0 define the time interval that starts after the first pulse detection. During this time interval, all pulses are ignored.
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6.10.6 0x28 PULSE_WIND register (Read/Write) Table 85. 0x28: PULSE_WIND Second Pulse Time Window register Bit 7 WIND7 Bit 6 WIND6 Bit 5 WIND5 Bit 4 WIND4 Back to Register Address Map Bit 3 WIND3 Bit 2 WIND2 Bit 1 WIND1 Bit 0 WIND0 Table 86.
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6.11 Auto-WAKE/SLEEP detection 6.11.1 0x29: ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write) The ASLP_COUNT register sets the minimum time period of inactivity required to switch the part between Wake and Sleep status. At the end of the time period, the device switches its ODR rate automatically when the Auto-WAKE /SLEEP function is enabled. • Wake ODR is set by CTRL_REG1[DR] bits. • Sleep ODR is set by CTRL_REG1[ASLP_RATE] bits.
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• Four interrupt sources can WAKE the device: Transient, Orientation, Tap, and the Motion/Freefall. One or more of these functions can be enabled. — To WAKE the device, the desired function(s) must be enabled in CTRL_REG4 register and set to WAKE-to-SLEEP in CTRL_REG3 register. — All enabled functions still run in SLEEP mode at the SLEEP ODR. Only the functions that have been selected for WAKE from SLEEP will actually WAKE the device (as configured in register 0x2C).
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Table 95. SLEEP mode rates ASLP_RATE1 ASLP_RATE0 Frequency (Hz) 0 0 50 0 1 12.5 1 0 6.25 1 1 1.56 Notes When the device is in Auto-SLEEP mode, the system ODR and the data rate for all the system functional blocks are overridden by the data rate set by the ASLP_RATE field. DR[2:0] bits select the Output Data Rate (ODR) for acceleration samples in WAKE mode. The default value is 000 for a data rate of 800 Hz. Table 96.
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6.12.2 0x2B: CTRL_REG2 System Control 2 register CTRL_REG2 register is used to enable Self-Test, Software Reset, and Auto-SLEEP. In addition, it enables you to configure the SLEEP and WAKE mode power scheme selection (oversampling modes). Table 98. 0x2B CTRL_REG2 register (Read/Write) Bit 7 ST Bit 6 RST Bit 5 0 Back to Register Address Map Bit 4 SMODS1 Bit 3 SMODS0 Bit 2 SLPE Bit 1 MODS1 Bit 0 MODS0 Table 99.
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Table 101. MODS Oversampling modes averaging values at each ODR Mode ODR (Hz) 6.12.3 Normal (00) Low Noise Low Power (01) High Resolution (10) Low Power (11) Current μA OS Ratio Current μA OS Ratio Current μA OS Ratio Current μA OS Ratio 1.56 27 128 9 32 184 1024 6.5 16 6.25 27 32 9 8 184 256 6.5 4 12.5 27 16 9 4 184 128 6.
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Table 103. CTRL_REG3 register (Continued) 0 PP_OD 6.12.4 Push-Pull/Open-Drain selection on interrupt pad Configures the interrupt pins to Push-Pull or to Open-Drain mode. The Open-Drain configuration can be used for connecting multiple interrupt signals on the same interrupt line. 0 Push-Pull (default) 1 Open Drain 0x2D: CTRL_REG4 Interrupt Enable register (Read/Write) CTRL_REG4 register enables the following interrupts: Auto-WAKE/SLEEP, Orientation Detection, Freefall/Motion, and Data Ready.
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6.13 Data calibration registers The 2’s complement offset correction registers values are used to realign the Zero-g position of the X, Y, and Z-axis after the device is mounted on a board. The resolution of the offset registers is 1.96 mg/LSB. The 2’s complement 8-bit value would result in an offset compensation range ±250 mg for each axis. 6.13.1 0x2F: OFF_X Offset Correction X register Table 108.
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7 Mounting Guidelines Surface mount printed circuit board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the Dual Flat No-Lead (DFN) package inertial sensors to PCBs.
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0.200 2x2 DFN Package 1.950 All measurements are in mm. 0.225 0.725 0.600 2.525 PCB landing pad Solder mask opening Package outline Figure 16. Package mounting measurements Table 114. Board mounting guidelines Description Value (mm) Landing Pad Width 0.225 Landing Pad Length 0.600 Solder Mask Pattern Width 0.725 Solder Mask Pattern Length 1.950 Landing Pad Extended Length 0.200 I/O Pads Extended Length 2.525 MMA8652FC Sensors Freescale Semiconductor, Inc.
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8 Tape and Reel 8.1 Tape dimensions Figure 17. Carrier tape 8.2 Device orientation Reel Pin 1 location Carrier tape User direction of feed Sprocket holes Cover tape Figure 18. Device orientation on carrier tape MMA8652FC 60 Sensors Freescale Semiconductor, Inc.
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9 Package Dimensions This drawing is located at http://cache.freescale.com/files/shared/doc/package_info/98ASA00301D.pdf. Figure 19. Case 98ASA00301D, 10-Lead DFN—page 1 MMA8652FC Sensors Freescale Semiconductor, Inc.
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Figure 20. Case 98ASA00301D, 10-Lead DFN—page 2 MMA8652FC 62 Sensors Freescale Semiconductor, Inc.
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Figure 21. Case 98ASA00301D, 10-Lead DFN—page 3 MMA8652FC Sensors Freescale Semiconductor, Inc.
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10 Revision History Table 115. Revision history for MMA8652FC Revision number Revision date 0 10/2012 • Initial release. 1.0 12/2012 • Classification changed to Technical Data. 2.0 02/2013 • Feature comparison table: Orientation Detection features (2) rewritten for clarification. • Section 1: Topics reordered for clarification and consistency. 3.0 06/2014 • Section 1.2: Updated Descriptions for Pins 3 and 4. • Section 6.6.2: Updated Description for Field SEL[1:0] in Table 32. • Section 6.12.
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