User guide
56 DSPAUDIOEVM Evaluation Board Users Manual MOTOROLA
This document contains information on a new product. Specifications and information herein are subject to change without notice.
org p:$100
START
main
ori #$03,mr ; mask interrupts
movep #$050003,x:M_PCTL ; DSP core at 24.576x4=98.28MHz
move #0,omr
movec #0,sp ; reset hardware stack pointer
movep #$000003,x:M_IPRP ; ESAI int’s enabled and top
priority
move #$40,r6 ; initialize stack pointer
move #>$FFFF,m6 ; linear addressing
move #>RX_BUFF_BASE,r0 ; initialize inputs, outputs to 0
move #>$FFFF,m0
move #0,x0
rep #4
move x0,x:(r0)+
move #>RX_BUFF_BASE,x0
move x0,x:RX_PTR
move #>TX_BUFF_BASE,x0
move x0,x:TX_PTR
;**************************************************************************
; Init ESAI
; FST/FSR and SCKT/SCKR are generated by the AKM AK4114 S/PDIF receiver
;**************************************************************************
movep #$000000,x:M_PCRC ;disable ESAI port
movep #$000000,x:M_PRRC
movep #$0c0200,x:M_TCCR ;init transmit clock control register
;FST is input (bit22=0)
;SCKT is driven externally (bit21=0)
;FST polarity is negative (bit19=1)
;clockout on falling, latch in on rising (bit18=1)
;2 words per frame (bit13:9=00001)
;all other bits are not relevant and are initialized to 0
movep #$0c0200,x:M_RCCR ;init receive clock control register
;FSR is input (bit22=0)
;SCKR is driven externally (bit21=0)
;FSR polarity is negative (bit19=1)
;clockout on falling, latch in on rising (bit18=0)
;2 words per frame (bit13:9=00001)
;all other bits are not relevant and are initialized to 0
movep #$000000,x:M_SAICR ;init ESAI common control register
;data left aligned to bit 23 (bit8=0)
;asynchronous mode (bit6=0)
;bits 23:9 and 5:3 are reserved and are initialized to 0
;all other bits are not relevant and are initialized to 0
movep #$d17d00,x:M_TCR
;init trasmit control register
;last slot interrupt enabled (bit23=1)
;transmit interrupt enabled (bit22=1)
;even slot interrupt disabled (bit21=0)
;exception interrupt enabled (bit20=1)
;transmitter normal operation (bit19=0)
;reserved (bit18=0)
;zero padding disabled (bit17=0)
;FS occurs 1 bit clock early (bit16=1)
;word length FS (bit15=0)
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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