Datasheet

Table 47. On-chip peripherals current consumption (continued)
Symbol Paramete
r
Conditions Value Unit
IDD_HV(FLASH) CFlash +
DFlash
supply
current on
VDD_HV_
ADC
VDD = 5.5
V
_ TBD mA
IDD_HV(PLL) PLL supply
current on
VDD_HV
VDD = 5.5
V
_ TBD
Debug specifications
4.6.1 JTAG interface timing
Table 48. JTAG pin AC electrical characteristics
1
# Symbol Characteristic Min Max Unit
1 t
JCYC
TCK Cycle Time
2
62.5 — ns
2 t
JDC
TCK Clock Pulse Width 40 60 %
3 t
TCKRISE
TCK Rise and Fall Times (40% - 70%) — 3 ns
4 t
TMSS
, t
TDIS
TMS, TDI Data Setup Time 5 — ns
5 t
TMSH
, t
TDIH
TMS, TDI Data Hold Time 5 — ns
6 t
TDOV
TCK Low to TDO Data Valid — 20
3
ns
7 t
TDOI
TCK Low to TDO Data Invalid 0 — ns
8 t
TDOHZ
TCK Low to TDO High Impedance — 15 ns
11 t
BSDV
TCK Falling Edge to Output Valid — 600
4
ns
12 t
BSDVZ
TCK Falling Edge to Output Valid out of High
Impedance
— 600 ns
13 t
BSDHZ
TCK Falling Edge to Output High Impedance — 600 ns
14 t
BSDST
Boundary Scan Input Valid to TCK Rising Edge 15 — ns
15 t
BSDHT
TCK Rising Edge to Boundary Scan Input Invalid 15 — ns
1. These specifications apply to JTAG boundary scan only.
2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Refer to pad specification for allowed transition frequency
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
4.6
Debug specifications
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
Freescale Semiconductor, Inc.
Preliminary
55