Datasheet

Table 42. MLB 3-Pin 256/512 Fs Timing Parameters (continued)
Parameter Symbol Min Max Unit Comment
MLBCLK low time
1
t
mck
l 30
14
— ns 256xFs
512xFs
MLBCLK high time t
mck
h 30
14
— ns 256xFs
512xFs
MLBSIG/MLBDAT receiver input setup to
MLBCLK falling
t
dsmcf
1 — ns —
MLBSIG/MLBDAT receiver input hold from
MLBCLK low
t
dhmcf
t
mcfdz
— ns —
MLBSIG/MLBDAT output valid from
MLBCLK low
t
mcfdz
0 t
mck
l ns 2
Bus output hold from MLBCLK low t
mdzh
4 — ns 2
1. MLBCLK low/high time includes the pluse width variation.
2. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final
driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the
maximum load capacitance listed.
Ground = 0.0 V; Load Capacitance = 40 pF, input transition= 1 ns; MediaLB speed =
1024 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as
listed below; unless otherwise noted.
Table 43. MLB 3-Pin 1024 Fs Timing Parameters
Parameter Symbol Min Max Unit Comme
nt
MLBCLK Operating Frequency
1
f
mck
45.056
-
-
51.2
MHz
MHz
1024 x fs
at 44.0
kHz
1024 x fs
at 50.0
kHz
MLBCLK rise time f
mckr
1 ns V
IL to
V
IH
MLBCLK fall time f
mckf
1 ns V
IH to
V
IL
MLBCLK low time t
mckl
6.1 — ns 2
MLBCLK high time t
mckh
9.3 — ns 2
MLBSIG/MLBDAT receiver input setup
to MLBCLK falling
t
dsmcf
1 — ns
MLBSIG/MLBDAT receiver input hold
from MLBCLK low
t
dhmcf
t
mcfdz
— ns
MLBSIG/MLBDAT output valid from
MLBCLK low
t
mcfdz
0 t
mckl
ns 3
Bus Hold from MLBCLK low t
mdzh
2 — ns 3
1. The controller can shut off MLBCLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLBCLK.
2. MLBCLK low/high time includes the pluse width variation.
MediaLB (MLB) electrical specifications
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
Freescale Semiconductor, Inc.
Preliminary
49