Datasheet

MII2 MII1
MII4MII3
Valid data
Valid data
Valid data
RXCLK (input)
RXD[n:0]
RXDV
RXER
Figure 22. RMII/MII receive signal timing diagram
4.4.4.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 40. RMII signal switching specifications
Num Description Min. Max. Unit
— EXTAL frequency (RMII input clock RMII_CLK) — 50 MHz
RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK
period
RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK
period
RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 — ns
RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 — ns
RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 — ns
RMII8 RMII_CLK to TXD[1:0], TXEN valid — 15 ns
MediaLB (MLB) electrical specifications
4.4.5.1 MLB 3-pin interface DC characteristics
The section lists the MLB 3-pin interface electrical characteristics.
Table 41. MediaLB 3-Pin Interface Electrical DC Specifications
Parameter Symbol Test Conditions Min Max Unit
Maximum input voltage — — — 3.6 V
Low level input threshold V
IL
— — 0.7 V
Table continues on the next page...
4.4.5
MediaLB (MLB) electrical specifications
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
Freescale Semiconductor, Inc.
Preliminary
47