Datasheet

PCSx
10
9
12
11
SCK Output
SCK Output
SIN
SOUT
First Data
Data
Last Data
First Data
Data
Last Data
(CPOL=0)
(CPOL=1)
Figure 12. DSPI modified transfer format timing — master, CPHA = 1
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5
6
9
11
10
SCK Input
First Data
Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
12
Figure 13. DSPI modified transfer format timing – slave, CPHA = 0
Communication interfaces
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
40
Preliminary
Freescale Semiconductor, Inc.