Datasheet

Data
Last Data
First Data
SIN
SOUT
12
11
10
Last Data
Data
First Data
SCK Output
SCK Output
PCSx
9
(CPOL=0)
(CPOL=1)
Figure 8. DSPI classic SPI timing — master, CPHA = 1
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5
6
9
11
10
12
SCK Input
First Data
Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
Figure 9. DSPI classic SPI timing — slave, CPHA = 0
Communication interfaces
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
38
Preliminary
Freescale Semiconductor, Inc.