Datasheet

NOTE

For numbers shown in the following figures, see Table 32

Table 33. Continuous SCK timing

Spec Characteristics Pad Drive/Load Value

Minimum Maximum

tSCK SCK cycle timing strong/50pf 100ns

PCS valid after SCK strong/50pf 15ns

PCS valid after SCK strong/50pf -4ns

Table 34. DSPI high speed mode I/Os

DSPI High speed SCK High speed SIN High speed SOUT

DSPI2 GPIO[78] GPIO[76] GPIO[77]

DSPI3 GPIO[100] GPIO[101] GPIO[98]

SPI1 GPIO[173] GPIO[175] GPIO[176]

SPI2 GPIO[79] GPIO[110] GPIO[111]

Data

Last Data

First Data

First Data Data Last Data

SIN

SOUT

PCSx

SCK Output

(CPOL=0)

(CPOL=1)

Figure 7. DSPI classic SPI timing — master, CPHA = 0

Communication interfaces

MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.

Freescale Semiconductor, Inc.

Preliminary