Datasheet

Table 32. DSPI electrical specifications (continued)
No Symbol Parameter Conditions High Speed Mode low Speed mode Unit
Min Max Min Max
9 t
SUI
Data setup
time for
inputs
Master (MTFE = 0) NA — 20 — ns
Slave 2 — 2 —
Master (MTFE = 1,
CPHA = 0)
15 — 8
1, 1
—
Master (MTFE = 1,
CPHA = 1)
15 — 20 —
10 t
HI
Data hold
time for
inputs
Master (MTFE = 0) NA — –5 — ns
Slave 4 — 4 —
Master (MTFE = 1,
CPHA = 0)
0 — 11
1
—
Master (MTFE = 1,
CPHA = 1)
0 — -5 —
11 t
SUO
Data valid
(after SCK
edge)
Master (MTFE = 0) — NA — 4 ns
Slave — 15 — 23
Master (MTFE = 1,
CPHA = 0)
— 4 — 16
1
Master (MTFE = 1,
CPHA = 1)
— 4 — 4
12 t
HO
Data hold
time for
outputs
Master (MTFE = 0) NA — –2 — ns
Slave 4 — 6 —
Master (MTFE = 1,
CPHA = 0)
-2 — 10
1
—
Master (MTFE = 1,
CPHA = 1)
–2 — –2 —
1. SMPL_PTR should be set to 1
NOTE
Restriction For High Speed modes
• DSPI2, DSPI3, SPI1 and SPI2 will support 40MHz Master
mode SCK
• DSPI2, DSPI3, SPI1 and SPI2 will support 25MHz Slave
SCK frequency
• Only one {SIN,SOUT and SCK} group per DSPI/SPI will
support high frequency mode
• For Master mode MTFE will be 1 for high speed mode
• For high speed slaves, their master have to be in MTFE=1
mode or should be able to support 15ns tSUO delay
Communication interfaces
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
36
Preliminary
Freescale Semiconductor, Inc.