Datasheet

4.3.6 Flash read wait state and address pipeline control settings
The following table describes the recommended RWSC and APC settings at various
operating frequencies based on specified intrinsic flash access times of the flash module
controller array at 125 °C.
Table 31. Flash Read Wait State and Address Pipeline Control Guidelines
Operating frequency (f
sys
)
1
RWSC APC Flash read latency on
mini-cache miss (# of
f
sys
clock periods)
Flash read latency on
mini-cache hit (# of
f
sys
clock periods)
40 MHz 1 0,1 3 1
80 MHz 2 0,1 5 1
120 MHz 3 0,1 6 1
160 MHz 4 0,1 7 1
1. Packaged parts (-40 to 150
o
C)
Communication interfaces
4.4.1 DSPI timing
Table 32. DSPI electrical specifications
No Symbol Parameter Conditions High Speed Mode low Speed mode Unit
Min Max Min Max
1 t
SCK
DSPI cycle
time
Master (MTFE = 0) 25 — 50 — ns
Slave (MTFE = 0) 40 — 60 —
2 t
CSC
PCS to SCK
delay
— 16 — — — ns
3 t
ASC
After SCK
delay
— 16 — — — ns
4 t
SDC
SCK duty
cycle
— t
SCK
/2 - 10 t
SCK
/2 + 10 — — ns
5 t
A
Slave access
time
SS active to SOUT
valid
— 40 — — ns
6 t
DIS
Slave SOUT
disable time
SS
inactive to SOUT
High-Z or invalid
— 10 — — ns
7 t
PCSC
PCSx to
PCSS time
— 13 — — — ns
8 t
PASC
PCSS to
PCSx time
— 13 — — — ns
Table continues on the next page...
4.4
Communication interfaces
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
Freescale Semiconductor, Inc.
Preliminary
35