Datasheet
1. Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 150 cycles, nominal voltage.
4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: -40°C ≤ T
J
≤ 150°C, full spec voltage.
4.3.2 Flash memory Array Integrity and Margin Read specifications
Table 28. Flash memory Array Integrity and Margin Read specifications
Symbol Characteristic Min Typical Max
1, 1
Units
2, 2
t
ai16kseq
Array Integrity time for sequential sequence on 16KB block. — — 512 x
Tperiod x
Nread
—
t
ai32kseq
Array Integrity time for sequential sequence on 32KB block. — — 1024 x
Tperiod x
Nread
—
t
ai64kseq
Array Integrity time for sequential sequence on 64KB block. — — 2048 x
Tperiod x
Nread
—
tai256kseq
Array Integrity time for sequential sequence on 256KB block. — — 8192 x
Tperiod x
Nread
—
t
mr16kseq
Margin Read time for sequential sequence on 16KB block. 73.81 — 110.7 μs
t
mr32kseq
Margin Read time for sequential sequence on 32KB block. 128.43 — 192.6 μs
t
mr64kseq
Margin Read time for sequential sequence on 64KB block. 237.65 — 356.5 μs
t
mr256kseq
Margin Read time for sequential sequence on 256KB block. 893.01 — 1,339.5 μs
1. Array Integrity times need to be calculated and is dependant on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
4.3.3 Flash memory module life specifications
Table 29. Flash memory module life specifications
Symbol Characteristic Conditions Min Typical Units
Array P/E
cycles
Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.
1, 1
— 250,000 — P/E
cycles
Number of program/erase cycles per block
for 256 KB blocks.
2, 2
— 1,000 250,000 P/E
cycles
Table continues on the next page...
Memory interfaces
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
32
Preliminary
Freescale Semiconductor, Inc.