Datasheet

Table 24. PLL electrical specifications
(continued)
Parameter Min Typ Max Unit Comments
Duty Cycle at pllclkout 48% (N+1)/
(2xN)
52% with even division at output with
odd division(N) at output
Regulator Maximum Output Current 0.75 mA
Analog Supply 1.08 1.2 1.32
Digital Supply (V
DD_LV
) 1.08 1.2 1.32
Period Jitter See Table 25 ps NON SSCG mode
TIE See Table 25 at 960 M Integrated over 1MHz
offset not valid in SSCG mode
Modulation Depth (Center Spread) +/- 0.25% +/- 4.0%
Modulation Depth (Down Spread) +/- 0.5% +/- 8.0%
Modulation Frequency 32 KHz
Lock Time 20 60 µs Calibration mode
10 30 µs Calibration bypass mode (wake-
up mode)
PLL reset assertion time 5 µs
Power Consumption 1 mA (avdd)
0.5 mA (dvdd)
at 1280 MHz VCO clock
T
A
=25°C
Table 25. Jitter calculation
Type of jitter Jitter due to
Supply
Noise (ps)
J
SN
1
Jitter due to
Fractional Mode
(ps) J
SDM
2
Jitter due to
Fractional Mode
J
SSCG
(ps)
3
1 Sigma
Random
Jitter J
RJ
(ps)
4
Total Period Jitter (ps)
Period Jitter 60 ps 3% of pllclkout1,2 Modulation depth 0.1% of
pllclkout1,2
+/-(J
SN
+J
SDM
+J
SSCG
+N
[4]
×J
RJ
Long Term Jitter
(Integer Mode)
N x J
RJ
Long Term jitter
(Fractional Mode)
N x J
RJ
1. This jitter component is due to self noise generated due to bond wire inductances on different PLL supplies. The jitter value
is valid for inductor value of 5nH or less each on avdd, avss, dvdd, dvss.
2. This jitter component is added when the PLL is working in the fractional mode.
3. This jitter component is added when the PLL is working in the Spread Spectrum Mode. Else it is 0.
4. The value of N is dependent on the accuracy requirement of the application. See Table 26.
Table 26. Percentage of sample exceeding specified value of jitter
N Percentage of samples exceeding specified value of jitter
(%)
1 31.73
2 4.55
3 0.27
Table continues on the next page...
Clocks and PLL interfaces modules
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
30
Preliminary
Freescale Semiconductor, Inc.