Datasheet

Table 19. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
V
H
Analog comparator hysteresis
1
CR0[HYSTCTR] = 0
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 20
CR0[HYSTCTR] = 30
0
10
20
30
mV
mV
mV
mV
V
CMPOh
Output high V
DD_HV_A
0.5
V
V
CMPOl
Output low 0.5 V
t
DHS
Propagation Delay, High Speed Mode (+/-100mV) 50 ns
Propagation Delay, High Speed Mode (+/-20mV) 120 ns
Analog comparator initialization delay, High Speed
Mode
2
4 μs
Analog comparator initialization delay, Low Power
Mode
100 μs
I
DAC6b
6-bit DAC current adder (when enabled)
3.3V Reference Voltage 6 9 μA
5V Reference Voltage 10 16 μA
INL 6-bit DAC integral non-linearity –0.5 0.5 LSB
3
DNL 6-bit DAC differential non-linearity –0.3 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to V
DD_HV_A
-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = V
reference
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Clocks and PLL interfaces modules
4.2.1 Main oscillator electrical characteristics
This device provides a driver for oscillator in pierce configuration with amplitude
control. Controlling the amplitude allows a more sinusoidal oscillation, reducing in this
way the EMI. Other benefits arises by reducing the power consumption. This Loop
Controlled Pierce (LCP mode) requires good practices to reduce the stray capacitance of
traces between crystal and MCU.
An operation in Full Swing Pierce (FSP mode), implemented by an inverter is also
available in case of parasitic capacitances and cannot be reduced by using crystal with
high equivalent series resistance. For this mode, a special care needs to be taken
regarding the serial resistance used to avoid the crystal overdrive.
4.2
Clocks and PLL interfaces modules
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
26
Preliminary
Freescale Semiconductor, Inc.