Datasheet

Table 6. Current consumption characteristics (continued)
Symbol Parameter Conditions
1
Min Typ Max Unit
I
DD_STOP
STOP mode
Operating current
T
a
= 25 °C
V
DD_LV
= 1.25 V
— 11 — mA
T
a
= 55 °C
V
DD_LV
= 1.25 V
— — TBD
T
a
= 125 °C
4
V
DD_LV
= 1.25 V
— — 160
I
DD_HALT
HALT mode
Operating current
T
a
= 25 °C
V
DD_LV
= 1.25 V
— — TBD mA
T
a
= 55 °C
V
DD_LV
= 1.25 V
— — TBD
T
a
= 125 °C
4
V
DD_LV
= 1.25 V
— — TBD
I
DD_HV_ADC_REF
11, 12
ADC REF
Operating current
T
a
= 25 °C
2 ADCs operating at 80 MHz
V
DD_HV_ADC_REF
= 3.6 V
— 200 400 µA
T
a
= 125 °C
4
2 ADCs operating at 80 MHz
V
DD_HV_ADC_REF
= 5.5 V
— 200 400
I
DD_HV_ADCx
12
ADC HV
Operating current
T
a
= 25 °C
ADC operating at 80 MHz
V
DD_HV_ADC
= 3.6 V
— 1 2 mA
T
a
= 125 °C
4
ADC operating at 80 MHz
V
DD_HV_ADC
= 5.5 V
— 1.2 2
I
DD_HV_FLASH
Flash Operating
current during
read access
T
a
= 125 °C
4
3.3 V supplies
x MHz frequency
— 40 45 mA
1. The content of the Conditions column identifies the components that draw the specific current.
2. ALL Modules enabled at maximum frequency: 2 x e200Z4 @160 MHz, e200Z2 at 80 MHz, Platform @160MHz, DMA
(SRAM to SRAM), all SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled), HSM
reading from flash at regular intervals (500 pll clock cycles), ENET0 transmitting, MLB transmitting, FlexRay transmitting,
USB-SPH transmitting (USB-OTG only clocked), 2 x I2C transmitting (rest clocked), 1 x SAI transmitting (rest clocked),
ADC0 converting using BCTU triggers triggered through PIT (other ADC clocked), RTC running, 3 x STM running, 2 x
DSPI transmitting (rest clocked), 2 x SPI transmitting (rest clocked), 4 x CAN state machines working(rest clocked), 9 x
LINFLEX transmitting (rest clocked), 1 x EMIOS clocked (used OPWFMB mode) (Others clock gated), SDHC,3 x CMP
only clocked, FIRC, SIRC, FXOSC, SXOSC, PLL running. All others modules clock gated if not specifically mentioned. I/O
supply current excluded.
3. Recommended Transistors:MJD31 @ 85°C, 105°C and 125°C.
4. Tj=150°C. Assumes Ta=125°C
• Assumes maximum θJA. SeeThermal attributes
5. Enabled Modules in Gateway mode: 2 x e200Z4 @160 MHz (Instruction and Data cache enabled), Platform @160MHz,
e200Z2 at 80 MHz(Instruction cache enabled), all SRAMs accessed in parallel, Flash access(prefetch is disabled while
buffers are enabled), HSM reading from flash at regular intervals(500 pll clock cycles), ENET0 transmitting, MLB
General
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
14
Preliminary
Freescale Semiconductor, Inc.