Datasheet

Table 4. Voltage regulator electrical specifications (continued)
Symbol Parameter Conditions Min Typ Max Unit
C
be_fpreg
Capacitor in parallel to base-
emitter
BCP68 and BCP56 3.3 nF
MJD31 4.7
C
flash_reg
3
External decoupling / stability
capacitor for internal Flash
regulators
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
1.32 2.2 3 µF
Combined ESR of external
capacitor
— 0.001 — 0.03 Ohm
C
HV_VDD_A
VDD_HV_A supply capacitor Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
1 — — µF
C
HV_ADC0
C
HV_ADC1
HV ADC supply decoupling
capacitances
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
1 — — µF
C
HV_ADR
HV ADC SAR reference supply
decoupling capacitances
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
0.47 — — µF
V
DD_HV_BALL
AST
FPREG Ballast collector supply
voltage
When collector of NPN ballast is
directly supplied by an on board
supply source (not shared with
VDD_HV_A supply pin) without
any series resistance, that is,
R
C_BALLAST
less than 0.01 Ohm.
2.25 — 5.5 V
R
C_BALLAST
Series resistor on collector of
FPREG ballast
When VDD_HV_BALLAST is
shorted to VDD_HV_A on the
board
— — 0.1 Ohm
t
SU
Start-up time after main supply
stabilization
Cfp_reg = 3 μF — 74 — μs
t
ramp
Load current transient Iload from 15% to 55%
C
fp_reg
= 3 µF
1.0 µs
1. Split capacitance on each pair VDD_LV pin should sum up to a total value of C
fp_reg
2. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and
maximum values.
3. It is required to minimize the board parasitic inductance from decoupling capacitor to VDD_HV_FLA pin and the routing
inductance should be less than 1nH.
General
MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
10
Preliminary
Freescale Semiconductor, Inc.