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MPC5748G

MPC5748G Microcontroller

Datasheet

Features

•

2 x 160 MHz Power Architecture® e200Z4 Dual issue,

32-bit CPU

– Single precision floating point operations

– 8 KB instruction cache and 4 KB data cache

– Variable length encoding (VLE) for significant code

density improvements

•

1 x 80 MHz Power Architecture® e200Z2 Single issue,

32-bit CPU

– Using variable length encoding (VLE) for

significant code size footprint reduction

•

End to end ECC

– All bus masters, for example, cores generate single

error correction, double error detection (SECDED)

code for every bus transaction

– SECDED covers 64-bit data and 29-bit address

•

Memory interfaces

– 6 MB on-chip flash supported with the flash

controller

– 3 x flash page buffers (3 port flash controller)

– 768 KB on-chip SRAM across three RAM ports

•

Clock interfaces

– 8-40 MHz external crystal (FXOSC)

– 16 MHz IRC (FIRC)

– 128 KHz IRC (SIRC)

– 32 KHz external crystal (SXOSC)

– Clock Monitor Unit (CMU)

– Frequency modulated phase-locked loop (FMPLL)

– Real Time Counter (RTC)

•

System Memory Protection Unit (SMPU) with up to 32

region descriptors and 16-byte region granularity

•

16 Semaphores to manage access to shared resource

•

Interrupt controller (INTC) capable of routing

interrupts to any CPU

•

Multiple crossbar switch architecture for concurrent

access to peripherals, flash, and RAM from multiple

bus masters

•

32-channels eDMA controller with multiple transfer

request sources using DMAMUX

•

Boot Assist Flash (BAF) supports internal flash

programming via a serial link (LIN / SCI)

•

Analog

– Two analog-to-digital converters (ADC), one 10-bit

and one 12-bit

– Three analogue comparators

– Cross Trigger Unit to enable synchronization of

ADC conversions with a timer event from the

eMIOS or from the PIT

•

Communication

– Four Deserial Peripheral Interface (DSPI)

– Six Serial Peripheral interface (SPI)

– 18 serial communication interface (LIN) modules

– Eight enhanced FlexCAN3 with FD support

– Four inter-IC communication interface (IIC)

– One USB OTG Controller (USB_0) and One USB

SPH Controller (USB_1) with ULPI Interface.

– ENET complex (10/100 Ethernet) that supports

Multi queue with AVB support, 1588, and MII/

RMII

– 2 x ENET with L2 switch

– Secure Digital Hardware Controller (uSDHC)

– Dual-channel FlexRay Controller

•

Audio

– 3 x Synchronous Audio Interface (SAI)

– Fractional clock dividers (FCD) operating in

conjunction with the SAIs

•

Configurable I/O domains supporting FLEXCAN,

LINFlex, Ethernet, USB, MLB, uSDHC and general I/

•

Supports wake-up from low power modes via the

WKUP controller

•

On-chip voltage regulator (VREG)

Freescale Semiconductor

Document Number: MPC5748G

Data Sheet: Advance Information

Rev. 2, 05/2014

This document contains information on a new product. Specifications and

information herein are subject to change without notice.

Preliminary

Summary of content (67 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5748G Rev.
PAGE 2
• Debug functionality – e200Z2 core:NDI per IEEE-ISTO 5001-2008 Class3+ – e200Z4 core(s): NDI per IEEE-ISTO 5001-2008 Class 3+ • Timer – 16 Periodic Interrupt Timers (PITs) – Three System Timer Module (STM) – Four Software WatchDog Timers (SWT) – 96 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels • Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) and 1149.
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Table of Contents 1 Ordering parts...........................................................................4 4.3.4 Data retention vs program/erase cycles................33 1.1 Determining valid orderable parts .....................................4 4.3.5 Flash memory AC timing specifications................34 1.2 Ordering Information .........................................................4 4.3.6 Flash read wait state and address pipeline 2 General................................................
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Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device number: MPC5748G . 1.2 Ordering Information P Example Code PC 57 4 8 G S K0 M MJ 6 R Qualification Status Power Architecture Automotive Platform Core Version Flash Size (core dependent) Product Optional fields Fab and mask indicator Temperature spec.
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General 2 General 2.1 Introduction The electrical specifications are preliminary and are initial evaluation. These specifications are not fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. 2.2 Absolute maximum ratings NOTE Functional operating conditions appear in the DC electrical characteristics.
PAGE 6
General Table 1. Absolute maximum ratings (continued) Conditions Min Max1 Unit Always –5 5 mA Absolute sum of all injected input currents during overload condition — –50 50 mA 0.5 V / min 100V/ms — Symbol Parameter IINJPAD Injected input current on any pin during overload condition IINJSUM Tramp Supply ramp rate — Ta8 Ambient temperature — -40 125 °C TSTG Storage temperature — –55 165 °C 1. Absolute maximum voltages are currently maximum burn-in voltages.
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General Table 2. Recommended operating conditions (VDD_HV_x = 3.3 V) (continued) Conditions Min1 Max Unit 3.3 V ADC supply ground — 0 0 V Internal supply voltage — 1.2 1.32 V VIN1_CMP_REF5, 6, 7 Analog Comparator DAC reference voltage — 3.15 3.6 6 V Symbol Parameter VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV5 VSS_LV Internal reference voltage — 0 0 V IINJPAD Injected input current on any pin during overload condition — -3.0 3.
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General Table 3. Recommended operating conditions (VDD_HV_x = 5 V) (continued) Conditions Min1 Max Unit Internal supply voltage — 1.2 1.32 V VSS_LV Internal reference voltage — 0 0 V IINJPAD Injected input current on any pin during overload condition — -3.0 3.0 mA Symbol Parameter VDD_LV4 TA5 Ambient temperature under bias fCPU ≤ 160 MHz –40 125 °C TJ Junction temperature under bias — –40 150 °C 1.
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General The following bipolar transistors1 are supported, depending on the device performance requirements.
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General Table 4. Voltage regulator electrical specifications (continued) Symbol Cbe_fpreg Cflash_reg3 Parameter Capacitor in parallel to baseemitter Conditions Min Typ BCP68 and BCP56 3.3 MJD31 4.7 External decoupling / stability capacitor for internal Flash regulators Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. Combined ESR of external capacitor — CHV_VDD_A VDD_HV_A supply capacitor CHV_ADC0 Unit nF 2.2 3 µF 0.001 — 0.
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General 2.5 Voltage monitor electrical characteristics Table 5. Voltage monitor electrical characteristics Symbol Parameter State Conditions Configuration Powe Mask r Up 1 Opt2, Reset Type Threshold Unit Min Typ Max V 0.930 0.979 1.028 V Trimmed 0.959 0.979 0.999 V Untrimmed 0.980 1.029 1.078 V Trimmed 1.009 1.029 1.
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General Table 5. Voltage monitor electrical characteristics (continued) Symbol Parameter State Conditions Configuration Powe Mask r Up 1 Opt2, Reset Type Threshold Min Typ Unit Max V 2 VLVD_IO_A_HI3 VLVD_FLASH VLVD_FLASH during low power mode using LPBG as reference4 HV IO_A supply low voltage monitoring high range Fall Trimmed No Rise Trimmed Flash supply low voltage monitoring Fall Untrimmed Yes Functional 4.
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General NOTE The ballast must be chosen in accordance with the ballast transistor supplier operating conditions and recommendations. Table 6. Current consumption characteristics Symbol IDD_FULL 2, 3 Conditions1 Parameter RUN Full Mode LV supply + HV supply + HV Flash supply + Operating current 2 x HV ADC supplies Min Typ Max Unit — 310 520 mA Ta = 85°C VDD_LV = 1.25 V VDD_HV_A = 5.
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General Table 6. Current consumption characteristics (continued) Symbol IDD_STOP Conditions1 Parameter STOP mode Ta = 25 °C Operating current VDD_LV = 1.25 V Ta = 55 °C Min Typ Max Unit — 11 — mA — — TBD — — 160 VDD_LV = 1.25 V Ta = 125 °C 4 VDD_LV = 1.25 V IDD_HALT HALT mode Ta = 25 °C Operating current VDD_LV = 1.25 V Ta = 55 °C — — TBD — — TBD — — TBD mA VDD_LV = 1.25 V Ta = 125 °C 4 VDD_LV = 1.
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General transmitting, FlexRay transmitting, USB-SPH Transmitting, USB-OTG clocked, 2 x I2C transmitting, (2 x I2C clock gated), 1 x SAI transmitting (2 x SAI clock gated), ADC0 converting in continuous mode (ADC1 clock gated), PIT clocked, RTC clocked, 3 x STM clocked, 2 x DSPI transmitting(Other DSPS clock gated), 2 x SPI transmitting(Other SPIs clock gated), 4 x FlexCAN state machines clocked(other FLEXCAN clock gated), 4 x LINFLEX transmitting (Other clock gated), 1x EMIOS clocked(used OPWFMB mode) (Othe
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General Table 8. STANDBY Current consumption characteristics (continued) Symbol STANDBY3 Conditions1 Parameter STANDBY with 256K RAM Ta = 25 °C Ta = 125 °C Min Typ Max Unit — 51.3 — µA — 5100 1. The content of the Conditions column identifies the components that draw the specific current. 2.7 Electrostatic discharge (ESD) characteristics Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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I/O parameters 3 I/O parameters 3.1 AC specifications @ 3.3 V Range Table 10. Functional Pad AC Specifications @ 3.3 V Range Prop. Delay (ns)1 Symbol Rise/Fall Edge (ns) Drive Load (pF) ipp_sre[1:0] L>H/H>L Min Max 1.5/1.5 25 2.5/2.5 7.5/7.5 0.9/0.9 3/3 50 6.4/5 19.5/19.5 3.5/2.5 12/12 200 2.2/2.5 8/8 0.6/0.8 3.5/3.5 25 pad_sr_hv Min 6/6 (output) Max MSB,LSB 11 10 0.090 1.1 0.035 1.1 asymmetry2 2.9/3.5 11.5/11.5 1.8/1.2 6.5/6.5 50 11/8 35/31 7.7/5 25/21 200 8.
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I/O parameters Table 11. DC electrical specifications @ 3.3V Range (continued) Symbol Value Unit Min Max Vih CMOS Input Buffer High Voltage (with hysteresis disabled) 0.55 * VDD_HV_x VDD_HV_x+ 0.3 V Vil CMOS Input Buffer Low Voltage (with hysteresis disabled) dVss - 0.3 0.40 * VDD_HV_x V Vhys Pull_Ioh CMOS Input Buffer Hysteresis 0.1 * VDD_HV_x Weak Pullup Current2 Current3 Pull_Iol Weak Pulldown Iinact_d Digital Pad Input Leakage Current (weak pull inactive) Voh Vol Ioh_f Iol_f 1.
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I/O parameters Table 12. Functional Pad AC Specifications @ 5 V Range (continued) Symbol Prop. Delay (ns)1 Rise/Fall Edge (ns) Drive Load (pF) ipp_sre[1:0] L>H/H>L Min Max pad_i_hv/pad_sr_hv Min 1.5/1.5 Max MSB,LSB 0.5/0.5 0.5 NA (input) 1. As measured from 50% of core side input to Voh/Vol of the output 2. Slew rate control modes 3.4 DC electrical specifications @ 5 V Range Table 13.
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I/O parameters 3.5 Functional reset pad electrical specifications The device implements a dedicated bidirectional RESET pin. AA A VDD_HV_IOx A VDDMIN PORST VIH VIL device reset forced by PORST device start-up phase Figure 2. Start-up reset requirements VPORST hw_rst VDD_HV_IO A ‘1’ VIH VIL ‘0’ filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter unknown reset state device under hardware reset WFRST WNFRST Figure 3.
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I/O parameters Table 14. Functional reset pad electrical specifications Symbol Parameter Conditions Value Min Unit Typ Max VIH Input high level TTL (Schmitt Trigger) — 2.0 — VDD_HV_A +0.4 V VIL Input low level TTL (Schmitt Trigger) — –0.4 — 0.8 V VHYS Input hysteresis TTL (Schmitt Trigger) — 300 — — mV VDD_POR Minimum supply for strong pull-down activation — — — 1.2 V IOL_R Strong pull-down current 1 Device under power-on reset 0.
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Peripheral operating requirements and behaviours 4 Peripheral operating requirements and behaviours 4.1 Analog 4.1.1 ADC electrical specifications The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter. Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 4090 ( 2) 1 LSB ideal =(VrefH-VrefL)/ 4096 = 3.3V/ 4096 = 0.806 mV Total Unadjusted Error TUE = +/- 6 LSB = +/- 4.
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Analog 4.1.1.1 Input impedance and ADC accuracy EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD_IO Source Filter RS Current Limiter RF Sampling RSW1 RAD RL CF VA Channel Selection CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 5. Input equivalent circuit Table 16.
PAGE 24
Analog Table 16. ADC conversion characteristics (for 12-bit) (continued) Symbol Conditions1 Parameter Min Typ Max Unit OFS Offset error — –6 — 6 LSB GNE Gain error — –4 — 4 LSB –6 +/-4 6 LSB <1 µs TUEIS1WINJ Total unadjusted error for IS1WINJ Without current injection STOP mode to Run mode recovery time 1. Recomended operating range, unless otherwise specified and analog input voltage from VSS_HV_ADC1 to VSS_HV_ADC_REF. 2.
PAGE 25
Analog Table 17. ADC conversion characteristics (for 10-bit) (continued) Symbol Conditions1 Parameter ADC Analog Pad (pad going to one ADC) TUEIS1WINJ Max leakage Min 150 °C Max positive/negative injection Total unadjusted error for IS1WINJ Without current injection Typ Max — — 250 nA –5 — 5 mA +/-3 4 LSB <1 µs –4 STOP mode to Run mode recovery time Unit 1. VDD = 3.3 V -5.5, TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VSS_HV_ADC0 to VDD_HV_ADC0.
PAGE 26
Clocks and PLL interfaces modules Table 19. Comparator and 6-bit DAC electrical specifications (continued) Symbol VH Description Min. Typ. Max. Unit • CR0[HYSTCTR] = 0 — 0 — mV • CR0[HYSTCTR] = 10 — 10 — mV • CR0[HYSTCTR] = 20 — 20 — mV • CR0[HYSTCTR] = 30 — 30 — mV Analog comparator hysteresis1 VCMPOh Output high VDD_HV_A – 0.5 — — V VCMPOl Output low — — 0.
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Clocks and PLL interfaces modules Other two modes called External (EXT Wave) and disable (OFF mode) are provided. For EXT Wave, the drive is disabled and an external source of clock within CMOS level based in analog oscillator supply can be used. When OFF, EXTAL is pulled down by 240 Kohms resistor and the feedback resistor remains active connecting XTAL through EXTAL by 1M resistor. Figure 6. Oscillator connections scheme Table 20.
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Clocks and PLL interfaces modules Table 20. Main oscillator electrical characteristics (continued) Symbol VXOSCHS TXOSCHSSU Parameter Oscillation Amplitude Startup time Mode Conditions LCP1, 2 FSP/LCP3 Supply current FSP LCP Min Typ Max Unit 4 MHz 1.0 8 MHz 1.0 16 MHz 1.0 40 MHz 0.8 4-40 MHz 1 ms 8 MHz 2.2 mA 16 MHz 2.2 40 MHz 3.2 8 MHz 141 16 MHz 252 40 MHz 518 VIH Input High EXT Wave level CMOS Schmitt trigger Oscillator supply=3.
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Clocks and PLL interfaces modules Table 22. 16 MHz RC Oscillator electrical specifications (continued) Symbol Parameter FUntrimmed Conditions Value Unit Min Typ Max IRC frequency (untrimmed) — 10.16 — 22.02 MHz IRC frequency variation after trimming — -5 — 5 % Tstartup Startup time — — 1 us TSTJIT Cycle to cycle jitter — — 1.5 % TLTJIT Long term jitter — — 0.02 % IVDDHV Current consumption on 3.
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Clocks and PLL interfaces modules Table 24. PLL electrical specifications (continued) Parameter Min Duty Cycle at pllclkout 48% Regulator Maximum Output Current 0.75 Analog Supply Digital Supply (VDD_LV) Typ Max (N+1)/ (2xN) 52% 1.08 1.2 1.32 1.08 1.2 1.32 Unit Comments with even division at output with odd division(N) at output mA Period Jitter See Table 25 TIE See Table 25 Modulation Depth (Center Spread) +/- 0.25% +/- 4.0% Modulation Depth (Down Spread) +/- 0.5% +/- 8.
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Memory interfaces Table 26. Percentage of sample exceeding specified value of jitter (continued) N Percentage of samples exceeding specified value of jitter (%) 4 6.30 × 1e-03 5 5.63 × 1e-05 6 2.00 × 1e-07 7 2.82 × 1e-10 4.3 Memory interfaces 4.3.1 Flash memory program and erase specifications NOTE All timing, voltage, and current numbers specified in this section are defined for a single embedded flash memory within an SoC, and represent average currents for given supplies and operations.
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Memory interfaces 1. Program times are actual hardware programming times and do not include software overhead. Block program times assume quad-page programming. 2. Typical program and erase times represent the median performance and assume nominal supply values and operation at 25 °C. Typical program and erase times may be used for throughput calculations. 3. Conditions: ≤ 150 cycles, nominal voltage. 4. Plant Programing times provide guidance for timeout limits used in the factory. 5.
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Memory interfaces Table 29. Flash memory module life specifications (continued) Symbol Data retention Characteristic Minimum data retention. Conditions Min Typical Units Blocks with 0 - 1,000 P/E cycles. 50 — Years Blocks with 100,000 P/E cycles. 20 — Years Blocks with 250,000 P/E cycles. 10 — Years 1. Program and erase supported across standard temperature specs. 2. Program and erase supported across standard temperature specs. 4.3.
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Memory interfaces 4.3.5 Flash memory AC timing specifications Table 30. Flash memory AC timing specifications Symbol Characteristic Min Typical Max Units Time from setting the MCR-PSUS bit until MCR-DONE bit is set to a 1. — 7 9.1 μs plus four system clock periods plus four system clock periods Time from setting the MCR-ESUS bit until MCR-DONE bit is set to a 1. — 16 20.
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Communication interfaces 4.3.6 Flash read wait state and address pipeline control settings The following table describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsic flash access times of the flash module controller array at 125 °C. Table 31.
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Communication interfaces Table 32.
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Communication interfaces NOTE For numbers shown in the following figures, see Table 32 Table 33. Continuous SCK timing Spec Characteristics Pad Drive/Load Value Minimum tSCK SCK cycle timing strong/50pf PCS valid after SCK strong/50pf PCS valid after SCK strong/50pf Maximum 100ns 15ns -4ns Table 34.
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Communication interfaces PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 Data First Data SIN Last Data 12 SOUT First Data 11 Data Last Data Figure 8. DSPI classic SPI timing — master, CPHA = 1 3 2 SS 1 4 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 12 11 Data Last Data Data Last Data 6 10 First Data Figure 9. DSPI classic SPI timing — slave, CPHA = 0 MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014. 38 Preliminary Freescale Semiconductor, Inc.
PAGE 39
Communication interfaces SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 SOUT First Data 9 SIN Data Last Data Data Last Data 10 First Data Figure 10. DSPI classic SPI timing — slave, CPHA = 1 3 PCSx 4 1 2 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 9 SIN First Data 10 12 SOUT First Data Last Data Data 11 Data Last Data Figure 11. DSPI modified transfer format timing — master, CPHA = 0 MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014. Freescale Semiconductor, Inc.
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Communication interfaces PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 10 9 SIN First Data Last Data Data 12 First Data SOUT 11 Last Data Data Figure 12. DSPI modified transfer format timing — master, CPHA = 1 3 2 SS 1 SCK Input (CPOL=0) 4 4 SCK Input (CPOL=1) SOUT First Data Data First Data 6 Last Data 10 9 SIN 12 11 5 Data Last Data Figure 13. DSPI modified transfer format timing – slave, CPHA = 0 MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014.
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FlexRay electrical specifications SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 First Data SOUT 9 Last Data Data Last Data 10 First Data SIN Data Figure 14. DSPI modified transfer format timing — slave, CPHA = 1 8 7 PCSS PCSx Figure 15. DSPI PCS strobe (PCSS) timing 4.4.2 FlexRay electrical specifications 4.4.2.1 FlexRay timing This section provides the FlexRay Interface timing characteristics for the input and output signals.
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FlexRay electrical specifications 4.4.2.2 TxEN TxEN 80 % 20 % dCCTxENFALL dCCTxENRISE Figure 16. TxEN signal Table 35.
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FlexRay electrical specifications PE_Clk TxEN dCCTxEN10 dCCTxEN01 Figure 17. TxEN signal propagation delays 4.4.2.3 TxD TxD dCCTxD50% 80 % 50 % 20 % dCCTxDRISE dCCTxDFALL Figure 18. TxD Signal Table 36. TxD output characteristics Name Description1 Min Max Unit dCCTxAsym Asymmetry of sending CC @ 25 pF load (=dCCTxD50% - 100 ns) –2.45 2.45 ns 92 ns dCCTxDRISE25+dCCTx Sum of Rise and Fall time of TxD signal at the output DFALL25 Table continues on the next page...
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FlexRay electrical specifications Table 36. TxD output characteristics (continued) Description1 Name Min Max Unit dCCTxD01 Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge 25 ns dCCTxD10 Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge 25 ns 1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +±10%, TJ = –40 °C / 150 °C, TxD pin load maximum 25 pF. 2. For 3.3 V ± 10% operation, this specification is 10 ns.
PAGE 45
FlexRay electrical specifications 1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +±10%, TJ = –40 oC / 150 oC. 4.4.3 uSDHC specifications Table 38. uSDHC switching specifications Num Symbol Description Min. Max. Unit Card input clock SD1 fpp Clock frequency (Identification mode) 0 400 kHz fpp Clock frequency (SD\SDIO full speed) 0 25 MHz fpp Clock frequency (SD\SDIO high speed) 0 40 MHz fpp Clock frequency (MMC full speed) 0 20 MHz fOD Clock frequency (MMC full speed) 0
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FlexRay electrical specifications 4.4.4 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 4.4.4.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. Table 39. MII signal switching specifications Symbol — MII1 Description RXCLK frequency RXCLK pulse width high Min.
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MediaLB (MLB) electrical specifications MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 22. RMII/MII receive signal timing diagram 4.4.4.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 40. RMII signal switching specifications Num — Description EXTAL frequency (RMII input clock RMII_CLK) Min. Max.
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MediaLB (MLB) electrical specifications Table 41. MediaLB 3-Pin Interface Electrical DC Specifications (continued) Parameter Symbol Test Conditions Min Max Unit High level input threshold VIH See Note1 1.8 — V Low level output threshold VOL IOL = –6 mA — 0.4 V High level output threshold VOH IOH = –6 mA 2.0 — V Input leakage current IL 0 < Vin < VDD — ±10 μA 1.
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MediaLB (MLB) electrical specifications Table 42.
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USB electrical specifications 3. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the maximum load capacitance listed. 4.4.6 USB electrical specifications 4.4.6.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum.
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USB electrical specifications U1 USB_CLKIN U2 U3 ULPI_DIR/ULPI_NXT (control input) ULPI_DATAn (input) U5 U4 ULPI_STP (control output) ULPI_DATAn (output) Figure 24. ULPI timing diagram 4.4.7 SAI electrical specifications All timing requirements are specified relative to the clock period or to the minimum allowed clock period of a device Table 45. Master mode SAI Timing no Parameter Value Unit Min Max Operating Voltage 2.7 3.
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USB electrical specifications Figure 25. Master mode SAI Timing Table 46. Slave mode SAI Timing No Parameter Value Unit Min Max Operating Voltage 2.7 3.
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USB electrical specifications Figure 26. Slave mode SAI Timing MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014. Freescale Semiconductor, Inc.
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On-chip peripherals 4.5 On-chip peripherals 4.5.1 On-chip peripherals Table 47.
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Debug specifications Table 47. On-chip peripherals current consumption (continued) Symbol Paramete r Conditions Value IDD_HV(FLASH) CFlash + VDD = 5.5 _ DFlash V supply current on VDD_HV_ ADC TBD IDD_HV(PLL) PLL supply VDD = 5.5 _ current on V VDD_HV TBD Unit mA 4.6 Debug specifications 4.6.1 JTAG interface timing Table 48. JTAG pin AC electrical characteristics 1 # Symbol Characteristic Time2 Min Max Unit 62.
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Debug specifications TCK 2 3 2 3 1 Figure 27. JTAG test clock input timing TCK 4 5 TMS, TDI 6 8 7 TDO Figure 28. JTAG test access port timing MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014. 56 Preliminary Freescale Semiconductor, Inc.
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Debug specifications TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 29. JTAG boundary scan timing 4.6.2 Nexus timing Table 49. Nexus debug port timing 1 No. Symbol Parameter 1 tMCYC MCKO Cycle Time 2 tMDC MCKO Duty Cycle MCKO Low to MDO, MSEO, EVTO Data Valid2 Condition s Min Max Unit — 15.6 — ns — 40 60 % — –0.1 0.25 tMCYC 3 tMDOV 4 tEVTIPW EVTI Pulse Width — 4 — tTCYC 5 tEVTOPW EVTO Pulse Width — 1 — tMCYC — 62.
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Debug specifications Table 49. Nexus debug port timing 1 (continued) No. Symbol Parameter Condition s Min Max Unit 9 tNTDIH, tNTMSH TDI, TMS Data Hold Time — 5 — ns 10 tJOV TCK Low to TDO/RDY Data Valid — 0 25 ns 1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. 2.
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Debug specifications 6 7 TCK 8 9 TMS, TDI 10 TDO/RDY Figure 32. Nexus TDI, TMS, TDO timing 4.6.3 WKUP/NMI timing Table 50. WKUP/NMI glitch filter No. Symbol Parameter Min Typ Max Unit 1 WFNMI NMI pulse width that is rejected — — 20 ns 2 WNFNMID NMI pulse width that is passed 400 — — ns MPC5748G Microcontroller Datasheet Data Sheet, Rev. 2, 05/2014. Freescale Semiconductor, Inc.
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Thermal attributes 4.6.4 External interrupt timing (IRQ pin) Table 51. External interrupt timing specifications No. Symbol Parameter Conditions Min Max Unit 1 tIPWL IRQ pulse width low — 3 — tCYC 2 tIPWH IRQ pulse width high — 3 — tCYC 3 tICYC IRQ edge to edge time — 6 — tCYC These values applies when IRQ pins are configured for rising edge or falling edge events, but not both. IRQ 1 2 3 Figure 33. External interrupt timing 5 Thermal attributes 5.
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Thermal attributes Board type Symbol Description Unit Notes Four-layer (2s2p) RθJMA Thermal 16 resistance, junction to ambient (200 ft./ min. air speed) °C/W 4 — RθJB Thermal 11 resistance, junction to board °C/W 5 — RθJCtop Thermal 8 resistance, junction to case top °C/W 6 — RθJCbotttom Thermal 0.5 resistance, junction to case bottom °C/W 7 — ΨJT Thermal 1 characterization parameter, junction to package top °C/W 8 1. 2. 3.
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Thermal attributes Board type Symbol Description — ΨJB Thermal 2.65 characterization parameter, junction to package top natural convection) 1. 2. 3. 4. 5. 6. 7. 324 MAPBGA Unit Notes °C/W 7 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
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Dimensions Board type Symbol Description — ΨJB Thermal 2.8 characterization parameter, junction to package top outside center (natural convection) 1. 2. 3. 4. 5. 6. 7. 256 MAPBGA Unit Notes °C/W 7 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
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Revision History 8 Revision History The following table provides a revision history for this document. Table 52. Revision History Rev. No. Date Substantial Changes Rev1 14 March 2013 Initial Release Rev1.1 16 May 2013 Updated Pinouts section Rev2 22 May 2014 • Removed Category (SR, CC, P, T, D, B) column from all the table of the Datasheet • Revised the feature list. • Revised Introduction section to remove classification information.
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Revision History Table 52. Revision History (continued) Rev. No. Date Substantial Changes • Revised Supply current characteristics section • Updated table: Current consumption characteristics • Updated table: Low Power Unit (LPU) Current consumption characteristics • STANDBY Current consumption characteristics • Revised Electromagnetic Interference (EMI) characteristics section • Revised DC electrical specifications @ 3.3V Range table for naming convections.
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Revision History Table 52. Revision History (continued) Rev. No.
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