Datasheet

Philips Semiconductors Product specification
TrenchMOS transistor BUK9575-100A
Logic level FET BUK9675-100A
Fig.11. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
Fig.12. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.13. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.14. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.15. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 25 A; parameter V
DS
Fig.16. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
0.5
1
1.5
2
2.5
3
-100 -50 0 50 100 150 200
Tmb / degC
a
Rds(on) normalised to 25degC
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.01 0.1 1 10 100
VDS/V
Capacitance / nF
Ciss
Coss
Crss
-100 -50 0 50 100 150 200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
1
2
3
4
5
0 5 10 15 20 25
QG / nC
VGS / V
VDS = 14V
VDS = 44V
0 0.5 1 1.5 2 2.5 3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2% typ
98%
0
10
20
30
40
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSDS/V
IF/A
25
Tj/C= 150
October 2000 5 Rev 1.200