DISCRETE SEMICONDUCTORS DATA SHEET BSS84 P-channel enhancement mode vertical D-MOS transistor Product specification Supersedes data of 1995 Apr 07 File under Discrete Semiconductors, SC13b 1997 Jun 18
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 FEATURES PINNING - SOT23 • Low threshold voltage PIN SYMBOL • Direct interface to C-MOS, TTL, etc. DESCRIPTION 1 g gate • High-speed switching 2 s source • No secondary breakdown. 3 d drain APPLICATIONS • Line current interrupter in telephone sets 3 handbook, halfpage d • Relay, high speed and line transformer drivers.
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER VDS drain-source voltage (DC) VGSO gate-source voltage (DC) ID drain current (DC) IDM peak drain current Ptot total power dissipation Tstg Tj CONDITIONS open drain MIN. MAX.
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 handbook, halfpage VDD = −40 V handbook, halfpage 10 % INPUT 90 % 10 % 0V OUTPUT ID −10 V 50 Ω 90 % ton MLD189 toff MBB690 Fig.2 Switching time test circuit. Fig.3 Input and output waveforms.
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 MLD191 80 MLD197 −600 handbook, halfpage handbook, halfpage C (pF) ID VGS = −10 V −7.5 V −6 V (mA) 60 −400 −5 V 40 Ciss 20 −4 V −200 Coss −3 V −2.5 V Crss 0 −10 0 −20 VDS (V) 0 −30 −2 0 −4 −6 −8 −10 −12 VDS (V) VGS = 0; Tj = 25 °C; f = 1 MHz. Tj = 25 °C. Fig.6 Capacitance as a function of drain source voltage; typical values. Fig.7 Typical output characteristics.
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 MLD195 1.2 MLD194 1.8 handbook, halfpage handbook, halfpage k k (1) (2) 1.0 1.4 0.8 1.0 0.6 −50 0 50 100 0.6 150 Tj (°C) −50 0 50 100 Tj (°C) 150 R DSon at T j k = ---------------------------------------R DSon at 25 °C V GSth at T j k = ------------------------------------V GSth at 25°C ID = −1 mA; VDS = VGS. (1) ID = −130 mA; VGS = −10 V. (2) ID = −20 mA; VGS = −2.4 V.
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 PACKAGE OUTLINE Plastic surface mounted package; 3 leads SOT23 D E B A X HE v M A 3 Q A A1 1 2 e1 bp c w M B Lp e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max. bp c D E e e1 HE Lp Q v w mm 1.1 0.9 0.1 0.48 0.38 0.15 0.09 3.0 2.8 1.4 1.2 1.9 0.95 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 NOTES 1997 Jun 18 9
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 NOTES 1997 Jun 18 10
Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS84 NOTES 1997 Jun 18 11
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