Datasheet

1997 Jun 20 3
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSP250
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. Pulse width and duty cycle limited by maximum junction temperature.
2. Device mounted on an epoxy printed-circuit board, 40 × 40 × 1.5 mm; mounting pad for drain lead minimum 6 cm
2
.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
drain-source voltage (DC) −−30 V
V
GSO
gate-source voltage (DC) open drain −±20 V
I
D
drain current (DC) T
s
≤ 100 °C −−3A
I
DM
peak drain current note 1 −−12 A
P
tot
total power dissipation T
s
= 100 °C − 5W
T
amb
=25°C; note 2 − 1.65 W
T
stg
storage temperature −65 +150 °C
T
j
operating junction temperature − 150 °C
Source-drain diode
I
S
source current (DC) T
s
≤ 100 °C −−1.5 A
I
SM
peak pulsed source current note 1 −−6A
Fig.2 Power derating curve.
handbook, halfpage
0 200
2.0
0
0.4
0.8
1.2
1.6
MLB885
T
amb
(°C)
50 100 150
P
tot
(W)
δ = 0.01.
Soldering point temperature T
s
= 100 °C.
(1) R
DSon
limitation.
Fig.3 SOAR.
handbook, halfpage
MLB835
V
DS
(V)
I
D
(A)
−10
−1
−10
2
−1 −10
−10
−2
−10
2
−10
−1
−1
−10
t
p
t
p
T
P
t
T
δ
=
1 ms
DC
(1)
t
p =
10 µs