Datasheet

NXP Semiconductors
88W8977
2.4 GHz/5 GHz Dual-band 1x1 Wi-Fi 4
®
and Bluetooth
®
5 Combo SoC
88W8977 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
Product short data sheet Rev. 1 — 13 July 2020
79 / 81
Tables
Tab. 1. Pad locations—74-bump eWLP ...................... 12
Tab. 2. Pin types ......................................................... 16
Tab. 3. General purpose I/O/LED interface ................. 17
Tab. 4. RF front-end control interface ......................... 19
Tab. 5. Wi-Fi/Bluetooth radio interface ........................ 19
Tab. 6. Bluetooth external coexistence interface ......... 20
Tab. 7. SDIO host interface .........................................21
Tab. 8. UART host interface (MFP) .............................21
Tab. 9. LTE interface ...................................................22
Tab. 10. PCM interface pins (MFP) ...............................22
Tab. 11. Power management interface pins (MFP) ....... 22
Tab. 12. Power supply and ground pins ........................23
Tab. 13. Clock interface ................................................ 23
Tab. 14. Power-down pin .............................................. 24
Tab. 15. JTAG interface pins (MFP) ..............................24
Tab. 16. Configuration pins ........................................... 25
Tab. 17. Firmware boot options .....................................25
Tab. 18. Absolute Maximum Ratings .............................32
Tab. 19. Recommended Operating Conditions ............. 33
Tab. 20. DC electricals—1.8V operation (VIO) ..............34
Tab. 21. DC electricals—2.5V operation (VIO) ..............34
Tab. 22. DC electricals—3.3V operation (VIO) ..............34
Tab. 23. LED Mode Data .............................................. 35
Tab. 24. DC electricals—1.8V operation (VIO_RF) ....... 36
Tab. 25. DC electricals—3.3V operation (VIO_RF) ....... 36
Tab. 26. 2.4 GHz Wi-Fi receiver performance ...............38
Tab. 27. 5 GHz Wi-Fi receiver performance ..................40
Tab. 28. 2.4 GHz Wi-Fi transmitter performance ...........42
Tab. 29. 5 GHz Wi-Fi transmitter performance ..............43
Tab. 30. Local oscillator ................................................ 43
Tab. 31. Bluetooth/Bluetooth LE receiver
performance .................................................... 45
Tab. 32. Bluetooth/Bluetooth LE transmitter
performance .................................................... 46
Tab. 33. Current consumption ....................................... 48
Tab. 34. DC electricals—1.8V operation (VIO_SD) ....... 50
Tab. 35. DC electricals—3.3V operation (VIO_SD) ....... 50
Tab. 36. SDIO timing data—Default speed mode and
high-speed modes (3.3V), ...............................52
Tab. 37. SDIO timing data——SDR12, SDR25,
SDR50 modes (up to 100 MHz) (1.8V) ........... 53
Tab. 38. SDIO timing data—DDR50 mode (50 MHz) .... 55
Tab. 39. UART timing data ............................................56
Tab. 40. PCM timing specification diagram for data
signals—Master mode .....................................57
Tab. 41. PCM timing specification diagram for sync
signal—Master mode ...................................... 57
Tab. 42. PCM timing specification data—Master
mode ............................................................... 57
Tab. 43. PCM timing specification diagram for data
signals—Slave mode .......................................58
Tab. 44. PCM timing specification diagram for sync
signal—Slave mode ........................................ 58
Tab. 45. PCM timing specification data—Slave mode ... 58
Tab. 46. CMOS mode ................................................... 59
Tab. 47. Low-Swing Mode .............................................59
Tab. 48. Phase Noise—2.4 GHz operation ................... 59
Tab. 49. Phase noise—Dual-band operation .................59
Tab. 50. Crystal specifications .......................................60
Tab. 51. External sleep clock timing ............................. 60
Tab. 52. JTAG timing data ............................................ 61
Tab. 53. Thermal conditions of QFN package ...............62
Tab. 54. Thermal conditions of eWLP package .............63
Tab. 55. Part Order Codes ............................................67
Tab. 56. Acronyms and abbreviations ...........................68
Tab. 57. Revision history ...............................................76
Figures
Fig. 1. 88W8977 functional block diagram ................... 2
Fig. 2. 88W8977 internal block diagram .......................4
Fig. 3. 88W8977 signal diagram ................................ 10
Fig. 4. Pin assignement for 68-pin package option
(top view) .........................................................11
Fig. 5. Pad locations—74-bump WLCSP (Non-
bump-side view, bumps down) ........................12
Fig. 6. Configuration—VCORE from PMIC .................27
Fig. 7. Configuration—VCORE from Internal LDO ..... 28
Fig. 8. Power-up sequence ........................................ 29
Fig. 9. Recommended power-down sequence ........... 30
Fig. 10. Power-down using PMIC_EN host pin -
PMIC and 88W8977 both in power-down
mode ............................................................... 31
Fig. 11. Slew rate measurement diagram .................... 35
Fig. 12. RF performance measurement points ............. 37
Fig. 13. SDIO protocol timing diagram—Default
speed mode (3.3V) ......................................... 51
Fig. 14. SDIO protocol timing diagram—High-speed
mode (3.3V) .................................................... 51
Fig. 15. SDIO protocol timing diagram—SDR12,
SDR25, SDR50 modes (up to 100 MHz)
(1.8V) ...............................................................53
Fig. 16. SDIO CMD timing diagram—DDR50 Mode
(50 MHz) ......................................................... 54
Fig. 17. SDIO DAT[3:0] timing diagram—DDR50
mode (50 MHz) ............................................... 54
Fig. 18. Figure Caption .................................................56
Fig. 19. JTAG timing diagram ...................................... 61
Fig. 20. 68-pin QFN package mechanical drawing .......64
Fig. 21. 74-bump package mechanical drawing ........... 65
Fig. 22. 68-pin QFN package marking and pin 1
location ............................................................ 66
Fig. 23. 74-bump eWLP package marking and pin 1
location ............................................................ 66
Fig. 24. Part numbering scheme .................................. 67