Datasheet

NXP Semiconductors
88W8977
2.4 GHz/5 GHz Dual-band 1x1 Wi-Fi 4
®
and Bluetooth
®
5 Combo SoC
88W8977 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
Product short data sheet Rev. 1 — 13 July 2020
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5.3.2 Power-down using PMIC_EN host pin
The maximum ramp-down time for VCORE from PMIC_EN assertion is 10 ms. PMIC_EN
must be asserted a minimum of 100 ms to guarantee that VCORE and AVDD18 are
discharged to less than 0.2V for the POR to generate properly after PMIC_EN is
deasserted.
Figure 10 shows the sequence.
VPA (2.2V)
AVDD18 (1.8V)/
PDn
VCORE (1.1V)
EN
(PMIC_EN)
Internal POR
min 100 ms
max 10 ms
Figure 10. Power-down using PMIC_EN host pin - PMIC and 88W8977 both in power-down mode
5.4 Deep sleep
When a programmable power regulator is used to supply VCORE, 88W8977 may use
the power management interface to reduce VCORE to approximately 0.8V to reduce the
power consumption in deep sleep mode.