Datasheet

74LVC4245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 18 December 2012 3 of 18
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration SO24 and (T)SSOP24 Fig 4. Pin configuration DHVQFN24
74LVC4245A
V
CC(A)
V
CC(B)
DIR V
CC(B)
A0 OE
A1 B0
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
GND B7
GND GND
001aaa349
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
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74LVC4245A
Transparent top view
B7
A7
GND
B6
GND
(1)
A6 B5
A5 B4
A4 B3
A3 B2
A2 B1
A1 B0
A0 OE
DIR V
CC(B)
GND GND
V
CC(A)
V
CC(B)
11 14
10 15
9 16
8 17
7 18
6 19
5 20
4 21
3 22
2 23
12 13
1
24
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
V
CC(A)
1 supply voltage (5 V bus)
V
CC(B)
23, 24 supply voltage (3 V bus)
GND 11, 12, 13 ground (0 V)
DIR 2 direction control
A[0:7] 3, 4, 5, 6, 7, 8, 9, 10 data input or output
B[0:7] 21, 20, 19, 18, 17, 16, 15, 14 data input or output
OE
22 output enable input (active LOW)