Datasheet

74HC_HCT86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 27 August 2012 3 of 16
NXP Semiconductors
74HC86; 74HCT86
Quad 2-input EXCLUSIVE-OR gate
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
86
1A V
CC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y
001aad103
1
2
3
4
5
6
7 8
10
9
12
11
14
13
Table 2. Pin description
Symbol Pin Description
1A to 4A 1, 4, 9, 12 data input
1B to 4B 2, 5, 10, 13 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function table
[1]
Input nA Input nB Output nY
LLL
LHH
HL H
HHL