Datasheet

1998 Feb 23 7
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
AC WAVEFORMS
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD
to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse
frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
handbook, full pagewidth
t
rem
t
W
t
W
t
PLH
t
rem
V
M
(1)
V
M
(1)
V
M
(1)
V
M
(1)
nQ OUTPUT
t
PHL
t
PLH
t
PHL
V
M
(1)
nR
D
INPUT
nS
D
INPUT
nCP INPUT
nQ OUTPUT
MGL350
Fig.7 Waveforms showing the set (nS
D
) and reset (nR
D
) input to output (nQ, nQ) propagation delays, the set
and reset pulse widths and the nR
D
, nS
D
to nCP removal time.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.