Datasheet

1998 Jun 04 13
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Fig.9 Waveforms showing the data set-up and hold times for the D
S
input.
(1) HC: V
M
= 50%; V
I
= GND to V
CC
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
handbook, full pagewidth
MLB196
t
h
t
su
t
h
t
su
Q
7
' OUTPUT
SH
CP
INPUT
D
S
INPUT
V
M
(1)
V
M
(1)
V
M
(1)
Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q
7
’) propagation delay
and the master reset to shift clock (SH
CP
) removal time.
(1) HC: V
M
= 50%; V
I
= GND to V
CC
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
handbook, full pagewidth
MLB197
t
PHL
t
W
V
M
(1)
V
M
(1)
V
M
(1)
SH
CP
INPUT
t
rem
MR INPUT
Q
7
' OUTPUT