Datasheet
December 1990 2
Philips Semiconductors Product specification
Octal D-type flip-flop; positive
edge-trigger; 3-state
74HC/HCT574
FEATURES
• 3-state non-inverting outputs for
bus oriented applications
• 8-bit positive edge-triggered
register
• Common 3-state output enable
input
• Independent register and 3-state
buffer operation
• Output capability: bus driver
• I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT574 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT574 are octal D-type
flip-flops featuring separate D-type
inputs for each flip-flop and
non-inverting 3-state outputs for bus
oriented applications. A clock (CP)
and an output enable (OE) input are
common to all flip-flops.
The 8 flip-flops will store the state of
their individual D-inputs that meet the
set-up and hold time requirements on
the LOW-to-HIGH CP transition.
When
OE is LOW, the contents of the
8 flip-flops are available at the
outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the flip-flops.
The “574” is functionally identical to
the “564”, but has non-inverting
outputs.
The “574” is functionally identical to
the “374”, but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
=C
PD
× V
CC
2
× f
i
+ ∑ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL/
t
PLH
propagation delay CP to Q
n
C
L
= 15 pF; V
CC
=5 V 1415ns
f
max
maximum clock frequency 123 76 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per flip-flop notes 1 and 2 22 25 pF