Datasheet

2003 Jun 17 2
Philips Semiconductors Product specification
Quad bilateral switches 74HC4066; 74HCT4066
FEATURES
• Very low ON-resistance:
–50Ω(typical) at V
CC
= 4.5 V
–45Ω(typical) at V
CC
= 6.0 V
–35Ω(typical) at V
CC
= 9.0 V.
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.
GENERAL DESCRIPTION
The 74HC4066 and 74HCT4066 are high-speed Si-gate
CMOS devices and are pin compatible with the
HEF4066B. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4066 and 74HCT4066 have four independent
analog switches. Each switch has two input/output pins
(pins nY or nZ) and an active HIGH enable input pin
(pin nE). When pin nE = LOW the belonging analog switch
is turned off.
The 74HC4066/74HCT4066 is pin compatible with the
74HC4016/74HCT4066 but exhibits a much lower
on-resistance. In addition, the on-resistance is relatively
constant over the full input signal range.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ[(C
L
+C
S
)×V
CC
2
× f
o
] where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
C
S
= maximum switch capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ[(C
L
+C
S
)×V
CC
2
× f
o
] = sum of the outputs.
2. For 74HC4066 the condition is V
I
= GND to V
CC
.
For 74HCT4066 the condition is V
I
= GND to V
CC
− 1.5 V.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
74HC4066 74HCT4066
t
PZH
/t
PZL
turn-on time nE to V
os
C
L
= 15 pF; R
L
=1kΩ; V
CC
=5V1112ns
t
PHZ
/t
PLZ
turn-off time nE to V
os
C
L
= 15 pF; R
L
=1kΩ; V
CC
=5V1316ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation
capacitance per switch
notes 1 and 2 11 12 pF
C
S
maximum switch
capacitance
88pF