Datasheet

December 1990 2
Philips Semiconductors Product specification
12-stage binary ripple counter 74HC/HCT4040
FEATURES
• Output capability: standard
• I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4040 are high-speed Si-gate CMOS
devices and are pin compatible with “4040” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4040 are 12-stage binary ripple counters
with a clock input (
CP), an overriding asynchronous
master reset input (MR) and twelve parallel outputs
(Q
0
to Q
11
). The counter advances on the HIGH-to-LOW
transition of CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
APPLICATIONS
• Frequency dividing circuits
• Time delay circuits
• Control counters
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
=C
PD
× V
CC
2
× f
i
+∑(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information” .
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay C
L
= 15 pF; V
CC
=5 V
CP to Q
0
14 16 ns
Q
n
to Q
n+1
88ns
f
max
maximum clock frequency 90 79 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 20 20 pF