Datasheet

December 1990 11
Philips Semiconductors Product specification
8-bit addressable latch 74HC/HCT259
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines” .
Fig.9 Waveforms showing the conditional reset input (MR) to output (Q
n
) propagation delays.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.11 Waveforms showing the address set-up and hold times for A
n
inputs to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.