Datasheet

ManualsBrandsNXP ManualsEmbedded Processors & Controllers8 Bit Latch D-Type SOIC

DATA SHEET

Product speciﬁcation

File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT259

8-bit addressable latch

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Summary of content (11 pages)

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT259 8-bit addressable latch Product specification File under Integrated Circuits, IC06 December 1990
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability The “259” also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE).
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2, 3 A0 to A2 address inputs 4, 5, 6, 7, 9 10, 11, 12 Q0 to Q7 latch outputs 8 GND ground (0 V) 13 D data input 14 LE latch enable input (active LOW) 15 MR conditional reset input (active LOW) 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 Fig.4 Functional diagram.
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES MR master reset L H X X X X L L L L L L L L L L L L L L L L d d d d L H L H L L H H L L L L Q=d L L L L Q=d L L L L Q=d L L L L Q=d L L L L L L L L L L L L L L L L L L L L L L L L d d d d L H L H L L H H H H H H L L L L L L L L L L L L L L L L Q=d L L L L Q=d L L L L Q=d L L L L Q=d H H X X X X q0 q1 q2 q3 q4 q5 q6 q7
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 Fig.5 Logic diagram.
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max.
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 TO +85 −40 TO +125 typ. max. min. max. min. WAVEFORMS UNIT V CC (V) max. tPHL/ tPLH propagation delay D to Qn 23 39 49 59 ns 4.5 Fig.7 tPHL/ tPLH propagation delay An to Qn 25 41 51 62 ns 4.5 Fig.8 tPHL/ tPLH propagation delay LE to Qn 22 38 48 57 ns 4.5 Fig.
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the enable input (LE) to output (Qn) propagation delays, the enable input pulse width and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the data input (D) to output (Qn) propagation delays and the output transition times.
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Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the conditional reset input (MR) to output (Qn) propagation delays. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.