Datasheet

ManualsBrandsNXP ManualsEmbedded Processors & ControllersDual AND Gate 74HC SOIC 33ns

1. General description

The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power

Schottky TTL (LSTTL).

The 74HC21 provide the 4-input AND function.

2. Features

n Low-power dissipation

n Complies with JEDEC standard no. 7A

n ESD protection:

u HBM JESD22-A114E exceeds 2000 V

u MM JESD22-A115-A exceeds 200 V

n Multiple package options

n Speciﬁed from −40 °Cto+80°C and from −40 °C to +125 °C.

3. Ordering information

74HC21

Dual 4-input AND gate

Rev. 05 — 7 May 2009 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC21N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HC21D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74HC21DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

74HC21PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

Summary of content (14 pages)

PAGE 1
74HC21 Dual 4-input AND gate Rev. 05 — 7 May 2009 Product data sheet 1. General description The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC21 provide the 4-input AND function. 2. Features n Low-power dissipation n Complies with JEDEC standard no. 7A n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specified from −40 °C to +80 °C and from −40 °C to +125 °C. 3.
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74HC21 NXP Semiconductors Dual 4-input AND gate 4. Functional diagram 1A 1 1B 2 1Y 1C 4 1 6 2 4 1D 5 9 10 2A 5 2B 9 2Y 2C 12 8 10 12 2D 13 13 1A 1B 6 1D 2A 2B 2Y 2C 8 2D 001aab975 Fig 1. 1Y 1C 001aab973 Functional diagram Fig 2. Logic symbol & 1 2 6 A 4 5 B & 9 10 Y 8 C 12 13 D 001aab974 Fig 3. IEC Logic symbol Fig 4. 001aab976 Logic diagram 5. Pinning information 5.1 Pinning 74HC21 1A 1 14 VCC 1B 2 13 2D n.c. 3 12 2C 1C 4 11 n.c.
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74HC21 NXP Semiconductors Dual 4-input AND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 1B, 1C, 1D 1, 2, 4, 5 data input n.c. 3, 11 not connected 1Y 6 data output GND 7 ground (0 V) 2Y 8 data output 2A, 2B, 2C, 2D 9, 10, 12, 13 data input VCC 14 supply voltage 6. Functional description Table 3.
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74HC21 NXP Semiconductors Dual 4-input AND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions VCC supply voltage Min Typ Max Unit 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V ∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.
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74HC21 NXP Semiconductors Dual 4-input AND gate 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure 8. Symbol Parameter propagation delay tpd transition time tt power dissipation capacitance CPD 25 °C Conditions −40 °C to +85 °C Min Typ Max Min Max Min Max VCC = 2.0 V - 33 110 - 140 - 165 ns VCC = 4.5 V - 12 22 - 28 - 33 ns [1] nA, nB, nC or nD to nY; see Figure 7 VCC = 6.0 V - 10 19 - 24 - 28 ns VCC = 5.
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74HC21 NXP Semiconductors Dual 4-input AND gate 11. Waveforms VI nA, nB, nC, nD input VM GND tPHL VOH nY output tPLH VY VM VX VOL tTHL tTLH 001aab977 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output transition times Measurement points Type 74HC21 Input Output VM VM VX VY 0.5VCC 0.5VCC 0.1VCC 0.
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4HC21 NXP Semiconductors Dual 4-input AND gate VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 8. Table 9.
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74HC21 NXP Semiconductors Dual 4-input AND gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.
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74HC21 NXP Semiconductors Dual 4-input AND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.
PAGE 10
74HC21 NXP Semiconductors Dual 4-input AND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.
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74HC21 NXP Semiconductors Dual 4-input AND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.
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74HC21 NXP Semiconductors Dual 4-input AND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11.
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74HC21 NXP Semiconductors Dual 4-input AND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74HC21 NXP Semiconductors Dual 4-input AND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . .