Datasheet

1998 Jul 08 7
Philips Semiconductors Product specification
Quad D-type flip-flop with reset; positive-edge trigger 74HC/HCT175
AC WAVEFORMS
Fig.6 Waveforms showing the clock (CP) to
outputs (Q
n
, Qn) propagation delays, the
clock pulse width, output transition times
and the maximum clock pulse frequency.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7 Waveforms showing the data set-up and
hold times for the data input (D
n
).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.8 Waveforms showing the master reset (MR)
pulse width, the master reset to outputs
(Q
n
, Q
n
) propagation delays and the master
reset to clock (CP) removal time.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.