Datasheet

1997 Nov 25 5
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” .
Output capability: standard
I
CC
category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL PARAMETER
T
amb
(°C) TEST CONDITIONS
74HC
UNIT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nCP to nQ, nQ
50
18
14
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.6
t
PLH
propagation delay
nS
D
to nQ
30
11
9
120
24
20
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.7
t
PHL
propagation delay
nS
D
to nQ
41
15
12
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.7
t
PHL
propagation delay
nR
D
to nQ
41
15
12
185
37
31
230
46
39
280
56
48
ns
2.0
4.5
6.0
Fig.7
t
PLH
propagation delay
nR
D
to nQ
39
14
11
170
34
29
215
43
37
255
51
43
ns
2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
19
7
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
W
set or reset pulse
width HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
t
rem
removal time
nS
D
,nR
D
to nCP
70
14
12
19
7
6
90
18
15
105
21
18
ns
2.0
4.5
6.0
Fig.7
t
su
set-up time
nJ, nK to nCP
70
14
12
17
6
5
90
18
15
105
21
18
ns
2.0
4.5
6.0
Fig.6
t
h
hold time
nJ, nK to nCP
5
5
5
0
0
0
5
5
5
5
5
5
ns
2.0
4.5
6.0
Fig.6
f
max
maximum clock
pulse frequency
6.0
30
35
22
68
81
5.0
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6