Datasheet

December 1990 6
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” .
Output capability: standard
I
CC
category: flip-flops
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
f
= t
f
= 6 ns; C
L
= 50 pF
INPUT UNIT LOAD COEFFICIENT
nK
nR
nCP, nJ
0.60
0.65
1.00
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nCP to nQ
19 36 45 54 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
nCP to nQ
21 36 45 54 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
nR to nQ, nQ
20 38 48 57 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.6
t
W
clock pulse width
HIGH or LOW
16 9 20 24 ns 4.5 Fig.6
t
W
reset pulse width
LOW
20 11 25 30 ns 4.5 Fig.7
t
rem
removal time
nR to nCP
14 8 18 21 ns 4.5 Fig.7
t
su
set-up time
nJ, nK to nCP
20 7 25 30 ns 4.5 Fig.6
t
h
hold time
nJ, nK to nCP
5 −2 5 5 ns 4.5 Fig.6
f
max
maximum clock pulse
frequency
30 66 24 20 MHz 4.5 Fig.6