Datasheet

December 1990 5
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” .
Output capability: standard
I
CC
category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL PARAMETER
T
amb
(°C) TEST CONDITIONS
74HC
UNIT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
nR to nQ, nQ
52
19
15
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
W
reset pulse width
LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
t
rem
removal time
nR to nCP
60
12
10
19
7
6
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
t
su
set-up time
nJ, nK to nCP
100
20
17
22
8
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.6
t
h
hold time
nJ, nK to nCP
3
3
3
−6
−2
−2
3
3
3
3
3
3
ns
2.0
4.5
6.0
Fig.6
f
max
maximum clock pulse
frequency
6.0
30
35
23
70
85
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6