Datasheet

December 1990 4
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
Fig.4 Functional diagram.
Fig.5 Logic diagram (one flip-flop).
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP
transition
X = don’t care
↓ = HIGH-to-LOW CP transition
OPERATING MODE
INPUTS OUTPUTS
nRnCP J K Q Q
asynchronous reset L X X X L H
toggle H ↓ hhqq
load “0” (reset) H ↓ IhL H
load “1” (set) H ↓ hIH L
hold “no change” H ↓ IIq
q