Datasheet

December 1990 2
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
FEATURES
• Output capability: standard
• I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (n
CP) and
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
= C
PD
× V
CC
2
× f
i
+∑(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
− 1.5 V.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information” .
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF;
V
CC
= 5 V
n
CP to nQ 16 16 ns
n
CP to nQ 1618ns
n
R to nQ, nQ 1617ns
f
max
maximum clock frequency 78 73 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation
capacitance per flip-flop
notes 1 and 2 30 30 pF