Datasheet

ManualsBrandsNXP ManualsEmbedded Processors & ControllersDual JK Flip-Flop with Clear SOIC 85MHz

DATA SHEET

Product speciﬁcation

File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT107

Dual JK flip-flop with reset;

negative-edge trigger

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Summary of content (8 pages)

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT107 Dual JK flip-flop with reset; negative-edge trigger Product specification File under Integrated Circuits, IC06 December 1990
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Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107 The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. FEATURES • Output capability: standard • ICC category: flip-flops The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
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Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 8, 4, 11 1J, 2J, 1K, 2K synchronous inputs; flip-flops 1 and 2 2, 6 1Q, 2Q complement flip-flop outputs 3, 5 1Q, 2Q true flip-flop outputs 7 GND ground (0 V) 12, 9 1CP, 2CP clock input (HIGH-to-LOW, edge-triggered) 13, 10 1R, 2R asynchronous reset inputs (active LOW) 14 VCC positive supply voltage Fig.1 Pin configuration.
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Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger Fig.4 Functional diagram. 74HC/HCT107 Fig.5 Logic diagram (one flip-flop). FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE nR asynchronous reset L nCP X J X K Q Q X L H toggle H ↓ h h q q load “0” (reset) H ↓ I h L H load “1” (set) H ↓ h I H L hold “no change” H ↓ I I q q Note 1.
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Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. −40 to +85 −40 to +125 typ. max. min. max. min. max.
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Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
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Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107 AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J and K to nCP set-up and hold times, the output transition times and the maximum clock pulse frequency.
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