Datasheet

ManualsBrandsNXP ManualsEmbedded Processors & ControllersQuad NAND Gate 74HC SOIC 25ns

DATA SHEET

Product speciﬁcation

Supersedes data of 1997 Aug 26

2003 Jun 30

INTEGRATED CIRCUITS

74HC00; 74HCT00

Quad 2-input NAND gate

Summary of content (17 pages)

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INTEGRATED CIRCUITS DATA SHEET 74HC00; 74HCT00 Quad 2-input NAND gate Product specification Supersedes data of 1997 Aug 26 2003 Jun 30
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V The 74HC00/74HCT00 provide the 2-input NAND function.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74HC00N −40 to +125 °C 14 DIP14 plastic SOT27-1 74HCT00N −40 to +125 °C 14 DIP14 plastic SOT27-1 74HC00D −40 to +125 °C 14 SO14 plastic SOT108-1 74HCT00D −40 to +125 °C 14 SO14 plastic SOT108-1 74HC00DB −40 to +125 °C 14 SSOP14 plastic SOT337-1 74HCT00DB −40 to +125 °C 14 SSOP14 plastic SOT337-1
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Philips Semiconductors Product specification Quad 2-input NAND gate handbook, halfpage 1A VCC 1 14 74HC00; 74HCT00 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND(1) handbook, halfpage A Y B Top view 7 8 GND 3Y MNA211 MNA950 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.2 Pin configuration DHVQFN14. Fig.3 Logic diagram (one gate).
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 RECOMMENDED OPERATING CONDITIONS 74HC00 SYMBOL PARAMETER 74HCT00 CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 − VCC 0 − VCC V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature +25 +125 −40 +25 +125 °C tr, tf input rise and fall times see DC and AC −40 characteristics per device VCC = 2.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 DC CHARACTERISTICS Type 74HC00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 VIH VIL VOH VOL 2.0 1.5 1.2 − V 4.5 3.15 2.4 − V 6.0 4.2 3.2 − V 2.0 − 0.8 0.5 V 4.5 − 2.1 1.35 V 6.0 − 2.8 1.8 V IO = −20 µA 2.0 1.9 2.0 − V IO = −20 µA 4.5 4.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level output voltage − − V 4.5 3.15 − − V 4.2 − − V 2.0 − − 0.5 V 4.5 − − 1.35 V 6.0 − − 1.8 V IO = −20 µA 2.0 1.9 − − V IO = −20 µA 4.5 4.4 − − V IO = −20 µA 6.0 5.9 − − V IO = −4.0 mA 4.5 3.7 − − V IO = −5.2 mA 6.0 5.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 Type 74HCT00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 VIH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − V VIL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 V VOH HIGH-level output voltage IO = −20 µA 4.5 4.4 4.5 − V IO = −4.0 mA 4.5 3.84 4.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 AC CHARACTERISTICS Type 74HC00 GND = 0 V; tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 tPHL/tPLH tTHL/tTLH propagation delay nA, nB to nY see Fig.6 2.0 − 25 115 ns see Fig.6 4.5 − 9 23 ns see Fig.6 6.0 − 7 20 ns 2.0 − 19 95 ns 4.5 − 7 19 ns 6.0 − 6 16 ns see Fig.6 2.0 − − 135 ns see Fig.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 AC WAVEFORMS handbook, halfpage VI VM nA, nB input GND tPHL tPLH VOH VM nY output VOL tTHL tTLH MNA218 74HC00: VM = 50%; VI = GND to VCC. 74HCT00: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 PACKAGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
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Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.
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Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.