Datasheet

MC68HC908GP20 — Rev 2.1 Advance Information
Freescale Semiconductor 363
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. (See 22.10.5 TIM
Channel Status and Control Registers.)
22.6 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests and TIM DMA service requests are
controlled by the channel x interrupt enable bit, CHxIE, and the
channel x DMA select bit, DMAxS. Channel x TIM CPU interrupt
requests are enabled when CHxIE:DMAxS = 1:0. Channel x
TIM DMA service requests are enabled when
CHxIE:DMAxS = 1:1. CHxF and CHxIE are in the TIM channel x
status and control register. DMAxS is in the TIM DMA select
register.
CAUTION: Because this chip does NOT have a DMA module, CHxIE bit should
NEVER be set when DMAxS is set. Doing so will mask TIM CPU
interrupt request and cause unwanted results.