Datasheet

MC68HC908GP20 — Rev 2.1 Advance Information
Freescale Semiconductor 357
22.5.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, TCLK. The prescaler generates seven clock rates from
the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register select the TIM clock source.
22.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
$0032
Timer 2 Channel 0
Register Low (T2CH0L)
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$0033
Timer 2 Channel 1 Status
and Control Register
(T2SC1)
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
$0034
Timer 2 Channel 1
Register High (T2CH1H)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0035
Timer 2 Channel 1
Register Low (T2CH1L)
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented
Figure 22-2. TIM I/O Register Summary (Sheet 3 of 3)