Datasheet

Advance Information MC68HC908GP20 — Rev 2.1
288 Freescale Semiconductor
19.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
19.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . .308
19.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .310
19.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . .311
19.2 Introduction
This section describes the system integration module (SIM). Together
with the CPU, the SIM controls all MCU activities. A block diagram of the
SIM is shown in Figure 19-1. Table 19-1 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that
coordinates CPU and exception timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 19-1 shows the internal signal names used in this section.