Datasheet

MC68HC908GP20 — Rev 2.1 Advance Information
Freescale Semiconductor 213
15.4.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and
the state of the PTC3 pin (when IRQ is set to V
TST
) upon entry into
monitor mode. When PTC3 is high, the divide by ratio is 1024. If the
PTC3 pin is at logic 0 upon entry into monitor mode, the divide by ratio
is 512.
If monitor mode was entered with V
DD
on IRQ, then the divide by ratio is
set at 1024, regardless of PTC3. If monitor mode was entered with V
SS
on IRQ, then the internal PLL steps up the external frequency, presumed
to be 32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor
mode entry require that the reset vector is blank.
Table 15-3 lists external frequencies required to achieve a standard
baud rate of 9600 BPS. Other standard baud rates can be accomplished
using proportionally higher or lower frequency generators. If using a
crystal as the clock source, be aware of the upper frequency limit that the
internal clock module can handle. See 23.8 5.0-V Control Timing and
23.9 3.0-V Control Timing for this limit.
15.4.5 Commands
The monitor ROM firmware uses these commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
Table 15-3. Monitor Baud Rate Selection
External
Frequency
IRQ
PTC3
Internal
Frequency
Baud Rate
(BPS)
4.9152 MHz V
TST
0 2.4576 MHz 9600
9.8304 MHz V
TST
1 2.4576 MHz 9600
9.8304 MHz V
DD
X 2.4576 MHz 9600
32.768 kHz V
SS
X 2.4576 MHz 9600