Datasheet

MC68HC908GP20 — Rev 2.1 Advance Information
Freescale Semiconductor 171
NOTE: A security feature prevents viewing of the FLASH contents.
1
11.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program, erase,
and margin read operations.
FDIV1 — Frequency Divide Control Bit
This read/write bit together with FDIV0 selects the value by which the
charge pump clock is divided from the system clock. See 11.5.1
FLASH Charge Pump Frequency Control.
FDIV0 — Frequency Divide Control Bit
This read/write bit together with FDIV1 selects the value by which the
charge pump clock is divided from the system clock. See 11.5.1
FLASH Charge Pump Frequency Control.
BLK1— Block Erase Control Bit
This read/write bit together with BLK0 allows erasing of blocks of
varying size. See 11.6 FLASH Erase Operation for a description of
available block sizes.
BLK0 — Block Erase Control Bit
This read/write bit together with BLK1 allows erasing of blocks of
varying size. See 11.6 FLASH Erase Operation for a description of
available block sizes.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Address: $FE08
Bit 7654321Bit 0
Read:
FDIV1 FDIV0 BLK1 BLK0 HVEN MARGIN ERASE PGM
Write:
Reset:00000000
Figure 11-1. FLASH Control Register (FLCR)