Datasheet

MC68HC908GP20 — Rev 2.1 Advance Information
Freescale Semiconductor 133
7.6.6 PLL Reference Divider Select Register
NOTE: PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the
programming information for the modulo reference divider.
RDS3–RDS0 — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects
the reference division factor, R. (See 7.4.3 PLL Circuits and 7.4.6
Programming the PLL.) RDS7–RDS0 cannot be written when the
PLLON bit in the PCTL is set. A value of $00 in the reference divider
select register configures the reference divider the same as a value of
$01. (See 7.4.7 Special Programming Exceptions.) Reset initializes
the register to $01 for a default divide value of 1.
NOTE: The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
NOTE: The default divide value of 1 is recommended for all applications.
PMDS7–PMDS4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
Address: $003B
Bit 7654321Bit 0
Read: 0000
RDS3 RDS2 RDS1 RDS0
Write:
Reset:00000001
= Unimplemented
Figure 7-9. PLL Reference Divider Select Register (PMDS)